FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verification

2026-03-06

IEEE VLSI Test Symposium

AI Summary

This work addresses the challenge of automatically translating natural language (NL) specifications into functionally correct SystemVerilog Assertions (SVAs), a task hindered by the syntactic complexity of SVA operators and the scarcity of high-quality training data, which limits the performance of large language models. To overcome these limitations, the authors propose FVRuleLearner, a novel framework that introduces the operator inference tree (Op-Tree)—a structured, interpretable representation that models NL-to-SVA translation as a stepwise reasoning process. By decomposing NL descriptions through operator-aware question parsing to construct Op-Trees and retrieving relevant reasoning paths during inference, FVRuleLearner significantly enhances assertion quality. Empirical results demonstrate a 3.95% improvement in syntactic correctness and a 31.17% gain in functional correctness over the current state of the art, along with an average 70.33% reduction in functional failures across diverse SVA operator categories.

Abstract

The remarkable reasoning and code generation capabilities of large language models (LLMs) have recently motivated increasing interest in automating formal verification (FV), a process that ensures hardware correctness through mathematically precise assertions but remains highly labor-intensive, particularly through the translation of natural language into SystemVerilog Assertions (NL-to-SVA). However, LLMs still struggle with SVA generation due to limited training data and the intrinsic complexity of FV operators. Consequently, a more efficient and robust methodology for ensuring correct SVA operator selection is essential for producing functionally correct assertions. To address these challenges, we introduce FVRuleLearner, an Operator-Level Rule (Op-Rule) learning framework built on a novel Operator Reasoning Tree (Op-Tree), which models SVA generation as structured, interpretable reasoning. FVRuleLearner operates in two complementary phases: (1) Training: it constructs Op-Tree that decomposes NL-to-SVA alignment into fine-grained, operator-aware questions, combining reasoning paths that lead to correct assertions; and (2) Testing: it performs operatoraligned retrieval to fetch relevant reasoning traces from the learned Op-Tree and generate new rules for unseen specifications. In the comprehensive studies, the proposed FVRuleLearner outperforms the state-of-the-art baseline by $3.95 \%$ in syntax correctness and by $31.17 \%$ in functional correctness on average. Moreover, FVRuleLearner successfully reduces an average of 70.33 % of SVA functional failures across diverse operator categories through a functional taxonomy analysis, showing the effectiveness of applying learned Op-Tree to the OpRule generations for unseen NL-to-SVA tasks. These results establish FVRuleLearner as a new paradigm for domain-specific reasoning and rule learning in formal verification. The source code and benchmark are available at https://github.com/NVlabs/FVRuleLearner.

Problem

• Formal Verification
• SystemVerilog Assertions
• Operator Selection
• NL-to-SVA
• Large Language Models

Innovation

• Operator-Level Reasoning Tree
• Formal Verification
• SystemVerilog Assertions
• Rule Learning
• NL-to-SVA