Low-Power PLL-Based Clock Stabilization for Flexible IGZO AMS Systems

2026-07-31

AI Summary

This work addresses the challenges of poor signal integrity and high power consumption in conventional clock generation schemes for flexible electronics, which suffer from significant process, voltage, and temperature (PVT) variations. The authors propose an ultra-low-power phase-locked loop (PLL) tailored for n-type amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors, achieving clock stability on a flexible platform that lacks p-type devices, exhibits limited carrier mobility, and experiences severe PVT drift. The PLL employs a lightweight charge-pump feedback loop to softly regulate a free-running ring oscillator, effectively suppressing long-term frequency drift without requiring a continuously active high-precision external reference. Operating across a 1 kHz–300 kHz output range, the system consumes only 0.115–0.153 mW in an area of 0.0115–0.0233 mm²—reducing power by over 400× and area by more than 1500× compared to existing solutions—while achieving a cycle jitter of 2.24 ns and long-term frequency accuracy within 1000 ppm.

Abstract

Flexible electronics (FE) platforms rely on analog and mixed-signal (AMS) circuits - biosensors, readout front-ends, and analog-to-digital converters - that dominate both functionality and energy consumption, making on-chip clock generation an essential yet power-critical function. Existing oscillator-based solutions suffer from unbounded process, voltage, and temperature (PVT) drift that degrades signal integrity, while alternative clock sources can consume up to 90% of the total system power budget, rendering them inapplicable to FE platforms and elevating clock generation to a primary power and energy-efficiency design constraint. This paper presents the first phase-locked loop (PLL) architecture designed for n-type-only amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) technology, addressing FE-specific constraints such as the absence of p-type devices, limited carrier mobility, and strong PVT variability. Rather than targeting high-precision frequency synthesis, the proposed design operates as a low-bandwidth temporal stabilizer: a free-running ring-oscillator-based voltage-controlled oscillator (VCO) is softly regulated by a minimal charge-pump feedback loop to bound long-term frequency drift without requiring a continuous high-quality external reference. The proposed PLL supports frequencies from 1 kHz to 300 kHz while occupying 0.0115-0.0233 mm2 and consuming 0.115-0.153 mW. Compared with prior oscillator-based FE clocking solutions, our architecture reduces power by more than 400x while achieving footprint reductions exceeding 1500x compared to flexible VCOs, and more than 390x with respect to ring-oscillator solutions. Validated across four representative published IGZO AMS systems, the proposed PLL achieves an rms period jitter of 2.24 ns and a long-term frequency accuracy within 1000 ppm, providing reference-anchored clock stability in FE platforms.

Problem

• flexible electronics
• clock generation
• power efficiency
• PVT variability
• IGZO AMS systems

Innovation

• PLL
• a-IGZO TFT
• low-power clocking
• flexible electronics
• frequency stabilization