Mitigating the Impact of Retention Loss on Inference Accuracy in 65 nm Single-Poly Floating-Gate Analog In-Memory Computing

2026-07-27

AI Summary

This work addresses the long-term inference accuracy degradation in 65 nm single-poly floating-gate analog in-memory computing chips caused by diminished charge retention. To mitigate this issue, the study introduces, for the first time, a circuit-algorithm co-compensation strategy that integrates circuit-level compensation—guided by statistical modeling of retention loss—with batch normalization recalibration. Evaluated on VGG-10/CIFAR-10 and WideResNet-28-10/CIFAR-100 models, the proposed approach restores inference accuracy to within 2–4% of the baseline even after 60 days of programming. This significant recovery demonstrates a marked enhancement in the long-term reliability and practicality of non-volatile analog in-memory computing systems.

Abstract

We show with experiments and system-level simulations that it is possible to successfully mitigate the impact of retention loss on inference accuracy degradation by using both circuit-level compensation techniques and batch normalization recalibration at the algorithmic level. Experiments are performed on a single-poly floating-gate (FG) analog non-volatile memory array for analog in-memory computing fabricated in a standard 65 nm CMOS. We use a model of retention-loss statistics calibrated with experiments to evaluate the system-level impact on neural network models such as VGG-10/CIFAR-10 and WideResNet-28-10/CIFAR-100. We show that, after 60 days since programming, combined mitigation techniques enable to recover the baseline inference accuracy within 2-4%

Problem

• retention loss
• inference accuracy
• analog in-memory computing
• floating-gate memory
• non-volatile memory

Innovation

• retention loss mitigation
• analog in-memory computing
• floating-gate memory
• batch normalization recalibration
• circuit-algorithm co-design