EquivFusion: Unifying Hardware Equivalence Checking from Algorithms to Netlists via MLIR

2026-04-17

AI Summary

This work addresses the challenge of verifying functional consistency between high-level algorithmic models and their low-level hardware implementations by proposing the first end-to-end equivalence verification framework based on MLIR. The framework employs a unified lowering pipeline to map diverse design sources—including PyTorch, C/C++, Chisel, Verilog, and gate-level netlists—into a common intermediate representation, which is then automatically translated into standard formal formats such as SMT-LIB, BTOR2, or AIGER. This enables automated pairwise equivalence checking across abstraction layers. For the first time, the approach establishes a complete formal verification flow spanning from algorithmic specifications to gate-level netlists, supporting a “shift-left” verification paradigm and demonstrating efficient, scalable cross-hierarchical verification capabilities, particularly for datapath-intensive designs.

Technology Category

Machine Learning: Hardware-aware MLComputer Vision: Low Level & Physics-based VisionKnowledge Representation and Reasoning: Automated Reasoning and Theorem Proving

Application Category

Systems and Infrastructure for Web, Mobile and WoT: Experiences and lessons learnt from Web-based algorithms and system deploymentsGraph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphsSemantics and Knowledge: Methods, algorithms and applications for the development of semantic models, knowledge graphs and other forms of structured data models with machine-interpretable semantics

Abstract

Ensuring functional consistency between high-level algorithmic models and low-level hardware implementations is a critical challenge, particularly as modern design flows increasingly span heterogeneous abstractions--from deep learning frameworks to hardware netlists. In this paper, we present EquivFusion, an end-to-end equivalence checking tool tailored for multi-modal circuit designs. Unlike traditional flows that rely on siloed tools or ad-hoc translation, EquivFusion leverages a verification-oriented MLIR lowering pipeline to unify diverse entry points, including PyTorch, C/C++, Chisel, Verilog, and gate-level netlists, into a common intermediate representation. This architecture enables automated, pairwise equivalence checking across diverse abstraction levels by rigorously translating designs into standard formal verification formats, i.e., SMT-LIB, BTOR2, AIGER. We demonstrate EquivFusion's feasibility to bridge the semantic gap between software specifications and hardware realizations, showcasing its effectiveness in facilitating "shift-left" formal verification for datapath-intensive hardware designs.

Problem

• equivalence checking
• hardware verification
• abstraction gap
• functional consistency
• formal verification

Innovation

• EquivFusion
• MLIR
• equivalence checking
• formal verification
• hardware-software co-verification