🤖 AI Summary
To address the trade-off between classification accuracy and area/power efficiency in printed ternary neural networks, this paper proposes the first automated design framework for printed ternary neural networks supporting arbitrary input precision. The method integrates analog-digital co-design, multi-objective evolutionary optimization, and full-system approximate computing to enable end-to-end joint optimization—from analog-to-digital interface to ternary classifier. Innovatively, it unifies analog front-end modeling with digital neural architecture search. Under a <5% accuracy degradation constraint, the framework achieves, on average, a 17× reduction in silicon area and a 59× reduction in power consumption. It enables, for the first time, a battery-powered, near-sensor intelligent processing system implemented entirely using printed electronics. This work establishes a scalable design paradigm for flexible, low-cost edge AI hardware.
📝 Abstract
Printed electronics offer a promising alternative for applications beyond silicon-based systems, requiring properties like flexibility, stretchability, conformality, and ultra-low fabrication costs. Despite the large feature sizes in printed electronics, printed neural networks have attracted attention for meeting target application requirements, though realizing complex circuits remains challenging. This work bridges the gap between classification accuracy and area efficiency in printed neural networks, covering the entire processing-near-sensor system design and co-optimization from the analog-to-digital interface-a major area and power bottleneck-to the digital classifier. We propose an automated framework for designing printed Ternary Neural Networks with arbitrary input precision, utilizing multi-objective optimization and holistic approximation. Our circuits outperform existing approximate printed neural networks by 17x in area and 59x in power on average, being the first to enable printed-battery-powered operation with under 5% accuracy loss while accounting for analog-to-digital interfacing costs.