Rendering 3D Gaussians on a Graph Processor

2026-07-17

AI Summary

This work addresses the challenges of bandwidth constraints, limited on-chip SRAM capacity, and workload imbalance in rendering 3D Gaussian splatting scenes on a DRAM-less graph processor (IPU) that relies solely on on-chip SRAM. It presents the first demonstration of SRAM-only 3D Gaussian rendering, deploying the task across an IPU composed of 1,472 tiles. By leveraging Manhattan-distance routing and a tree-based distribution strategy, Gaussian primitives are dynamically assigned to corresponding screen regions based on spatial locality, with computation synchronized under the Bulk Synchronous Parallel (BSP) model. This approach substantially reduces off-chip memory traffic, validates the feasibility of DRAM-free rendering, and elucidates the impact of bandwidth, SRAM capacity, and Gaussian density distribution on both performance and visual quality, offering a new paradigm for real-time rendering on edge-sensor platforms.

Abstract

We present the first implementation of a 3D Gaussian renderer on an Intelligence Processing Unit (IPU), comprising 1,472 independent tiles with only on-chip SRAM; constraints that approximate properties of efficient sensor-processor architectures. Our input scenes are 3D Gaussian maps from real-world sequences. Each tile 'owns' a screen-space region of the framebuffer; Gaussian primitives are routed to destination tiles via Manhattan-distance hops on a north-east-west-south (NEWS) grid, then distributed to overlapping neighbours in an expanding tree pattern. Computation follows the IPU's Bulk Synchronous Parallel (BSP) model, with inter-tile communication defined at compile time. We show this hardware allows us to exploit spatial and temporal locality by enabling local data transfer between cores. We evaluate the bottlenecks in this SRAM-only implementation: inter-tile bandwidth, per-tile SRAM capacity, and workload imbalance from non-uniform Gaussian density. We analyse how these constraints affect performance and render quality. This exploration raises broader questions for conventional GPUs and 3D representations, suggesting that direct inter-SM (streaming multiprocessor) communication might offer ways to reduce DRAM access in GPU kernels. We discuss these implications for the future of on-sensor and DRAM-free architectures. Project page: https://nmjfry.github.io/ipu-3dgs/

Problem

• 3D Gaussian rendering
• on-chip SRAM
• inter-tile communication
• workload imbalance
• sensor-processor architecture

Innovation

• 3D Gaussian Splatting
• Intelligence Processing Unit (IPU)
• On-chip SRAM
• Bulk Synchronous Parallel (BSP)
• Tile-based Rendering