Kalyna Block Cipher: From Design Space Exploration to ASIC Design

2026-07-24

AI Summary

This work addresses the lack of efficient and secure ASIC implementations for the Kalyna block cipher by proposing a hardware architecture optimized for area, latency, and energy consumption. The design integrates countermeasures—including operation randomization, masking, and time redundancy—to simultaneously mitigate side-channel analysis and fault injection attacks. Multiple ASIC prototypes supporting encryption, decryption, and a unified datapath were fabricated and validated in a 65 nm CMOS process. Experimental results demonstrate that the proposed implementation significantly reduces hardware overhead while effectively concealing power leakage and enhancing robustness against physical attacks.

Abstract

The Kalyna block cipher is a Ukrainian cryptography standard, selected through a national competition held between 2007 and 2010 and approved in 2015. Although its software implementations have been introduced, hardware-efficient implementations of the algorithm, i.e., accelerators, do not exist. In this paper, we explore various design architectures to implement its encryption, decryption, and unified encryption/decryption functions, considering the trade-off between area and latency. We present hardware reduction techniques and introduce alternative designs with low area, latency, and energy consumption, targeting an application-specific integrated circuit (ASIC). We present hardware-efficient designs that include countermeasures against side-channel analysis (SCA) and fault injection (FI) attacks, such as hiding, masking, and duplication techniques. We validate these implementations in a 65\;nm ASIC chip. Experimental results confirm the need for alternative designs that explore the design search space for different requirements. The proposed architectures enable hiding the power SCA leakage by randomizing the execution of operations, and the temporal duplication in designs with countermeasures against the SCA attacks can mitigate the FI attacks. The functionality of the ASIC test chip, including various Kalyna designs, is validated through measurements.

Problem

• Kalyna block cipher
• hardware-efficient implementation
• ASIC design
• side-channel analysis
• fault injection

Innovation

• Kalyna block cipher
• ASIC implementation
• side-channel countermeasures
• design space exploration
• fault injection protection