X-OPM: Explainable Automatic Digital On-Chip Power Modeling for Enhanced Robustness

2026-10-06

AI Summary

This study addresses the lack of physical interpretability and insufficient cross-workload generalization in existing on-chip power consumption models by proposing a robust feature engineering framework grounded in VLSI design principles. Methodologically, it introduces a human-in-the-loop workflow to balance modeling accuracy against overhead, integrating tree-based models to capture nonlinear interactions with linear models for prediction, while leveraging EDA tools for layout verification. Experimental results demonstrate that the proposed model achieves an R² exceeding 0.93 with an area overhead below 0.1%. It outperforms state-of-the-art methods such as APOLLO in predictive accuracy and maintains stable generalization performance under previously unseen workloads.

Abstract

Proactive power management systems reduce processor dynamic power through runtime power prediction and power-aware scheduling. Accurate, stable and low-overhead digital on-chip power meters (OPMs) are crucial for improving the prediction quality. Recent studies have explored various modeling methods, including using linear models, decision trees, and multi-layer perceptrons (MLPs) to construct OPMs. However, most current approaches train models end-to-end without analyzing the physical interpretability of features, affecting their ability to generalize to unseen workloads. Grounded in the design principles of synchronous digital VLSI circuits, X-OPM introduces a robust feature engineering framework that uses tree-based models to capture feature interactions and linear models for prediction. It also incorporates a human-in-the-loop workflow to balance model accuracy against modeling effort. Evaluated on a commercial C906 vector processor, X-OPM consistently achieves $R^2 > 0.93$ across all workloads with sampling window size set below $8$ cycles. In contrast, state-of-the-art methods including APOLLO, COBIT, and standard MLPs fail to generalize across all test cases. Layout with commercial EDA tools shows that X-OPM incurs an area overhead below $0.1\%$, which is on par with lightweight tree-based and linear models, and significantly smaller than MLP-based models.

Problem

• on-chip power modeling
• generalization
• physical interpretability
• power prediction
• robustness

Innovation

• Explainable Power Modeling
• Feature Engineering
• On-Chip Power Meter
• Tree-based Models
• Human-in-the-loop