Scholar
Thomas Benz
Google Scholar ID: OjbmkZkAAAAJ
ETH Zurich
Digital Designs
High-Performance SoCs
Memory Architectures
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Citations & Impact
All-time
Citations
289
H-index
9
i10-index
9
Publications
20
Co-authors
62
list available
Publications
13 items
Scalable AXI4 Transaction Monitoring for Mixed-Criticality SoCs: From Phase-Level Precision to ID-Level Efficiency
2026
Cited
0
Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
2026
Cited
0
HyperCroc: End-to-End Open-Source RISC-V MCU with a Plug-In Interface for Domain-Specific Accelerators
2026
Cited
0
Implementing and Optimizing an Open-Source SD-card Host Controller for RISC-V SoCs
2026
Cited
0
Development of an Energy-Efficient and Real-Time Data Movement Strategy for Next-Generation Heterogeneous Mixed-Criticality Systems
2026
Cited
0
Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond
2025
Cited
0
A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
2025
Cited
0
Data-Driven Power Modeling and Monitoring via Hardware Performance Counter Tracking
2025
Cited
0
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Co-authors
14 total
Luca Benini
ETH Zürich, Università di Bologna
Paul Scheffler
ETH Zurich
Frank K. Gürkaynak
Senior Scientist, ETH Zurich
Matheus Cavalcante
Stanford University
Davide Rossi
Associate Professor, University Of Bologna
Torsten Hoefler
Professor of Computer Science at ETH Zurich
Michael Rogenmoser
ETH Zurich
Salvatore Di Girolamo
NVIDIA
