Scholar
Paul Scheffler
Google Scholar ID: BI54jSkAAAAJ
ETH Zurich
Computer Architecture
Digital Hardware Design
Interconnects
ASICs
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Citations & Impact
All-time
Citations
166
H-index
8
i10-index
8
Publications
20
Co-authors
37
list available
Publications
10 items
Implementing and Optimizing an Open-Source SD-card Host Controller for RISC-V SoCs
2026
Cited
0
HyperCroc: End-to-End Open-Source RISC-V MCU with a Plug-In Interface for Domain-Specific Accelerators
2026
Cited
0
Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond
2025
Cited
0
Co-designing a Programmable RISC-V Accelerator for MPC-based Energy and Thermal Management of Many-Core HPC Processors
2025
Cited
0
Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS
2025
Cited
0
SpikeStream: Accelerating Spiking Neural Network Inference on RISC-V Clusters with Sparse Computation Extensions
2025
Cited
0
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications
2025
Cited
0
Croc: An End-to-End Open-Source Extensible RISC-V MCU Platform to Democratize Silicon
2025
Cited
0
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Co-authors
15 total
Luca Benini
ETH Zürich, Università di Bologna
Thomas Benz
ETH Zurich
Frank K. Gürkaynak
Senior Scientist, ETH Zurich
Luca Bertaccini
ETH Zurich
Matheus Cavalcante
Stanford University
Torsten Hoefler
Professor of Computer Science at ETH Zurich
Nils Wistoff
PhD Student, ETH Zurich
Luca Colagrande
PhD student, ETH Zurich
