Scholar
Xiaowen Wang
Google Scholar ID: aDdcc-oAAAAJ
Vanderbilt University, Silicon Labs
Circuit Designs
Fault Tolerance
Better-Than-Worst-Case Design
Timing Analysis
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Citations & Impact
All-time
Citations
103
H-index
4
i10-index
4
Publications
6
Co-authors
0
Publications
8 items
Learning from Research: Toward Lifelong Agent Harness Evolution
2026
Cited
0
Persistent Context Graphs for Efficient Memory Compaction in LLM Agents
2026
Cited
0
Stashbird: Efficient Speaker-Indexed Memory for Conversational Agents
2026
Cited
0
RAFT: A Stateful Retrieval-Augmented Framework for Troubleshooting Agents
2026
Cited
0
GroupMemBench: Benchmarking LLM Agent Memory in Multi-Party Conversations
2026
Cited
0
CT-Conditioned Diffusion Prior with Physics-Constrained Sampling for PET Super-Resolution
2026
Cited
0
Towards Reliable Pediatric Brain Tumor Segmentation: Task-Specific nnU-Net Enhancements
2025
Cited
0
A Survey of Datasets for Information Diffusion Tasks
arXiv.org · 2024
Cited
1
