convert schematic to netlist

Machine learning–generated circuit netlists suffer from poor readability and debuggability, hindering their practical adoption in hardware design. To address this, we propose the first large language model (LLM) specialized for circuit design, enabling end-to-end automatic conversion of netlists into LTSpice (.asc) schematics and CircuitTikZ (LaTeX) diagrams. Methodologically, we pioneer the use of LLMs for joint semantic and topological mapping from netlists to schematics; introduce circuit-domain knowledge–enhanced instruction tuning, structure-aware tokenization, and format-constrained decoding; and incorporate compiler feedback via multi-stage supervised fine-tuning. Experiments demonstrate that our model achieves a 93% LaTeX compilation success rate—significantly surpassing state-of-the-art general-purpose and code-specific LLMs (26%)—and attains structural similarity three times higher than human-designed reference schematics, markedly improving topological fidelity and engineering utility.

Existing methods for converting circuit schematic images into EDA-processable netlists suffer from poor generalizability across IC and PCB domains, inaccurate component recognition, ambiguous connectivity inference, and frequent misinterpretation of crossing wires. This work proposes the first fully automated parsing pipeline that integrates deep learning, connected-component labeling, OCR, and vision-language models to precisely extract components, labels, and topological connections. A dedicated crossing-wire detection module is introduced to distinguish genuine electrical junctions from mere graphical overlaps. The approach unifies processing for both IC and PCB schematics and achieves a netlist accuracy of 96.67% on real-world datasets—2.72 times higher than the current state-of-the-art—while ensuring functional equivalence through graph isomorphism verification.

Existing methods for converting SPICE netlists into human-readable schematics lack guarantees of connectivity correctness and suffer from significantly degraded accuracy as circuit complexity increases. This work proposes a deterministic conversion approach based on Sugiyama’s layered graph layout, integrating an embedded pinout database of 5,093 LTspice symbols and a round-trip connectivity verification mechanism. For the first time, this method enables netlist-to-schematic translation with a binary correctness certificate, ensuring network-by-network equivalence between the generated schematic and the original netlist. Implemented as a client-side, single-file, dependency-free architecture, the approach achieves 100% compilation success and connectivity verification pass rates on the Circuits-LTSpice benchmark and demonstrates an 88.4% verification pass rate on Analog Devices’ official dataset of 3,460 circuits.

This work proposes an end-to-end automated system to address the challenges of inaccurate component recognition and connectivity inference in the conversion of circuit schematic images into machine-readable netlists. The approach synergistically integrates deep learning, connected-component labeling (CCL), optical character recognition (OCR), and a vision-language model (VLM). Notably, it pioneers the use of VLM for component label assignment, enabling more reliable semantic understanding of schematic elements. Through the coordinated application of these complementary techniques, the system achieves high-fidelity netlist generation. Experimental results demonstrate an overall accuracy of 96.47%, representing a 2.72-fold improvement over the current state-of-the-art method.

Existing image-to-netlist conversion methods for analog schematics suffer from limited compatibility with diverse schematic styles and insufficient coverage of analog component types. To address these limitations, this paper proposes Image2Net—the first end-to-end framework supporting multi-style, multi-type analog components. Methodologically, it integrates deep learning–driven image recognition and structural parsing, rule-guided topological inference, and semantic consistency verification. We also introduce the first open-source schematic dataset featuring diversity and balanced complexity. Innovatively, we propose Netlist Edit Distance (NED) as a precision metric for quantitative evaluation. Experimental results demonstrate that Image2Net achieves an 80.77% conversion success rate on benchmark tests—surpassing state-of-the-art methods by 34.62–45.19%. Its average NED of 0.116 outperforms existing approaches by 62.1–69.6%, confirming substantial gains in structural and semantic fidelity.

This work addresses the inefficiency and error-proneness of manual symbol and footprint creation in traditional PCB design by proposing SFgen, a novel pipeline that leverages agent-driven multimodal large language models for automated recognition and generation of electronic component symbols and footprints. The approach introduces SFnet, an extensible component library that has already integrated 1,000 components and continues to expand. Experimental results demonstrate that SFgen achieves 86% accuracy in symbol generation and 80% accuracy in footprint generation, significantly enhancing the automation level of PCB design and the efficiency of component library construction.

This work addresses the ongoing challenge of automatically translating natural language specifications into editable printed circuit board (PCB) schematics for embedded and IoT development. It presents the first end-to-end approach that leverages tool-augmented large language model reasoning, integrating component library retrieval, datasheet knowledge extraction, execution validation, and structural-semantic verification to generate KiCad-compliant schematics. The system supports iterative refinement through an interactive web interface and achieves a pass@1 rate of 0.90 and a pass@5 rate of 1.00 across 20 embedded schematic generation tasks. This method efficiently produces high-quality initial drafts suitable for early-stage prototype review, substantially advancing the state of hardware design automation.

This work addresses the longstanding challenge in PCB schematic design, which heavily relies on manual effort and lacks effective methods for automatically generating editable circuit diagrams from natural language. We propose SchGen, the first large language model tailored for this task, introducing a novel semantic-anchored code representation that reframes the geometry-driven generation problem as a semantic matching task. To support training, we construct a large-scale paired dataset linking natural language descriptions to schematics. SchGen integrates pin-name-aware routing with relative component layout to enable end-to-end generation of editable schematics from text. Experimental results demonstrate that SchGen significantly outperforms existing representation schemes and even larger general-purpose language models in terms of wiring accuracy and functional correctness, highlighting the critical role of domain-specific semantic representations in complex hardware generation tasks.

This study addresses the limitations of traditional Design Structure Matrix (DSM) modularization approaches, which rely solely on graph-based optimization and lack engineering semantic context, often failing to align with practical design requirements. The authors propose a novel DSM modularization paradigm integrating large language models (LLMs), leveraging prompt engineering and iterative refinement to embed system-level semantic information directly into the partitioning process—achieving high-quality results without custom optimization code. Central to this work is the "semantic alignment hypothesis," which elucidates how improper incorporation of domain knowledge can degrade performance. Through systematic experiments across five representative engineering cases using three mainstream LLMs, the method demonstrates convergence to reference-quality modularization within 30 iterations, offering a reproducible and practical pathway for LLM-driven engineering design optimization.