electrical schematic design

Existing methods for converting circuit schematic images into EDA-processable netlists suffer from poor generalizability across IC and PCB domains, inaccurate component recognition, ambiguous connectivity inference, and frequent misinterpretation of crossing wires. This work proposes the first fully automated parsing pipeline that integrates deep learning, connected-component labeling, OCR, and vision-language models to precisely extract components, labels, and topological connections. A dedicated crossing-wire detection module is introduced to distinguish genuine electrical junctions from mere graphical overlaps. The approach unifies processing for both IC and PCB schematics and achieves a netlist accuracy of 96.67% on real-world datasets—2.72 times higher than the current state-of-the-art—while ensuring functional equivalence through graph isomorphism verification.

This work addresses the challenges in automated PCB schematic design, which are hindered by heterogeneous signal processing, difficulties in modeling realistic IC package constraints, and a lack of open-source datasets and validation methodologies. The authors propose the first training-free framework for automatic schematic generation, integrating large language model agents with constraint-guided synthesis. By leveraging domain-specific prompts, the system iteratively generates circuit code and constructs a knowledge graph derived from IC datasheets to enable precise validation of both topological structure and pin semantics. The approach supports mixed-signal designs encompassing digital, analog, and power circuits, demonstrating significant improvements in design accuracy and computational efficiency across 23 real-world tasks, thereby establishing a novel training-free paradigm for PCB schematic generation.

Machine learning–generated circuit netlists suffer from poor readability and debuggability, hindering their practical adoption in hardware design. To address this, we propose the first large language model (LLM) specialized for circuit design, enabling end-to-end automatic conversion of netlists into LTSpice (.asc) schematics and CircuitTikZ (LaTeX) diagrams. Methodologically, we pioneer the use of LLMs for joint semantic and topological mapping from netlists to schematics; introduce circuit-domain knowledge–enhanced instruction tuning, structure-aware tokenization, and format-constrained decoding; and incorporate compiler feedback via multi-stage supervised fine-tuning. Experiments demonstrate that our model achieves a 93% LaTeX compilation success rate—significantly surpassing state-of-the-art general-purpose and code-specific LLMs (26%)—and attains structural similarity three times higher than human-designed reference schematics, markedly improving topological fidelity and engineering utility.

Existing methods for converting SPICE netlists into human-readable schematics lack guarantees of connectivity correctness and suffer from significantly degraded accuracy as circuit complexity increases. This work proposes a deterministic conversion approach based on Sugiyama’s layered graph layout, integrating an embedded pinout database of 5,093 LTspice symbols and a round-trip connectivity verification mechanism. For the first time, this method enables netlist-to-schematic translation with a binary correctness certificate, ensuring network-by-network equivalence between the generated schematic and the original netlist. Implemented as a client-side, single-file, dependency-free architecture, the approach achieves 100% compilation success and connectivity verification pass rates on the Circuits-LTSpice benchmark and demonstrates an 88.4% verification pass rate on Analog Devices’ official dataset of 3,460 circuits.

This work addresses the challenges of deploying natural language–to–circuit diagram generation, which often suffers from hallucinated details, violations of electrical constraints, and non-machine-readable outputs. The authors propose a multi-agent LLM-assisted design framework that translates natural language instructions into structured, verifiable circuit schematics through a five-stage pipeline: component identification, pin retrieval, expert reasoning, JSON synthesis, and SVG visualization. Integrating an embedded component knowledge base, chain-of-thought reasoning, and the CircuitJSON format, the method introduces a novel dual-metric circuit verification (DMCV) mechanism to guarantee both electrical and topological correctness. Experimental evaluation on 100 embedded-system prompts demonstrates strong performance in microcontroller-related designs, enabling reliable translation from natural language to high-fidelity, deployable hardware specifications.

为解决AI驱动的PCB设计自动化中缺乏大规模配对数据集的问题，通过构建包含300多个实际设计的PCBnet数据集，并开发自动化的原理图到网表转换流程。

This work addresses the ongoing challenge of automatically translating natural language specifications into editable printed circuit board (PCB) schematics for embedded and IoT development. It presents the first end-to-end approach that leverages tool-augmented large language model reasoning, integrating component library retrieval, datasheet knowledge extraction, execution validation, and structural-semantic verification to generate KiCad-compliant schematics. The system supports iterative refinement through an interactive web interface and achieves a pass@1 rate of 0.90 and a pass@5 rate of 1.00 across 20 embedded schematic generation tasks. This method efficiently produces high-quality initial drafts suitable for early-stage prototype review, substantially advancing the state of hardware design automation.

This work addresses the longstanding challenge in PCB schematic design, which heavily relies on manual effort and lacks effective methods for automatically generating editable circuit diagrams from natural language. We propose SchGen, the first large language model tailored for this task, introducing a novel semantic-anchored code representation that reframes the geometry-driven generation problem as a semantic matching task. To support training, we construct a large-scale paired dataset linking natural language descriptions to schematics. SchGen integrates pin-name-aware routing with relative component layout to enable end-to-end generation of editable schematics from text. Experimental results demonstrate that SchGen significantly outperforms existing representation schemes and even larger general-purpose language models in terms of wiring accuracy and functional correctness, highlighting the critical role of domain-specific semantic representations in complex hardware generation tasks.

本文探讨了大型语言模型在电子设计自动化中的角色转变，从生成器到协调器，并提出需要一个标准化、物理感知的协调器来解决现有方法难以扩展到工业设计的问题。

This work addresses the inefficiency and error-proneness of manual symbol and footprint creation in traditional PCB design by proposing SFgen, a novel pipeline that leverages agent-driven multimodal large language models for automated recognition and generation of electronic component symbols and footprints. The approach introduces SFnet, an extensible component library that has already integrated 1,000 components and continues to expand. Experimental results demonstrate that SFgen achieves 86% accuracy in symbol generation and 80% accuracy in footprint generation, significantly enhancing the automation level of PCB design and the efficiency of component library construction.