correct-by-construction synthesis

This work addresses safety hazards in G-code generation caused by physical collisions and the lack of formal verification by proposing a self-correcting generation framework that integrates a neural language model (GLLM) with a separation logic verifier. For the first time, separation logic is applied to neural code generation, modeling physical space via a Spatial Heap and interpreting collisions as spatial resource conflicts. When verification fails, the framework provides precise feedback based on minimum bounding boxes to guide the GLLM in iteratively refining its output. This approach enables the automatic synthesis of provably collision-free G-code, substantially reducing manual intervention and enhancing the safety and reliability of autonomous manufacturing systems.

Traditional formal verification lacks mechanisms for knowledge accumulation and cross-system reuse, making it difficult to transfer specifications, contracts, and proofs. This work proposes a novel paradigm that integrates artificial intelligence with formal methods, pioneering the combination of large language models and graph-based representations to enable semantic guidance across heterogeneous notations and abstraction levels. By leveraging automated contract synthesis, semantic artifact reuse, and compositional refinement theory, the authors construct a hybrid reasoning framework that ensures formal reliability while supporting continuous synthesis and migration of verification artifacts. This approach lays the foundation for a cumulative and evolvable verification ecosystem, paving the way toward scalable, knowledge-driven next-generation verification systems.

Reactive synthesis faces dual challenges of high algorithmic complexity and the difficulty of writing formal specifications. This work proposes a neurosymbolic approach that, for the first time, incorporates natural language specifications into reactive synthesis by leveraging a large reasoning model to generate Verilog circuits and integrating a model checker to provide symbolic feedback for iterative refinement. The method establishes an end-to-end natural synthesis pipeline that outperforms existing specialized tools on benchmarks from the annual synthesis competition. Notably, it achieves performance comparable to hand-crafted formal specifications when using natural language inputs and scales to the synthesis of undecidable parameterized systems.

This work addresses the frequent failures of electronic design automation (EDA) code generated by large language models (LLMs), which often arise from violations of implicit structural dependencies among design entities—such as invalid paths, missing preconditions, or API incompatibilities. To overcome the high latency and poor scalability of existing tool-in-the-loop debugging approaches, the authors propose a novel framework for reliable code generation that operates without runtime feedback. The key innovation lies in explicitly modeling structural dependencies as execution contracts and guiding a validator-driven synthesis process via a structural dependency graph. This approach integrates graph-conditioned retrieval, constraint generation, and staged pre-execution validation. Empirical results demonstrate a single-step task pass rate of 82.5%, an improvement in multi-step task success from 30.0% to 84.0%, over twofold reduction in tool invocations, and a validator precision of 93.3% (6.7% false positive rate).

This work addresses the lack of formal correctness guarantees in code generated by large language models (LLMs), which hinders compliance with safety-critical software certification standards such as DO-178C, IEC 61508, and ISO 26262. To bridge this gap, the authors propose Forge, a closed-loop pipeline that integrates model-driven engineering with multiple formal verification techniques—including Dafny for deductive verification, FDR4 for CSP refinement checking, and Isabelle for Z-Machine theorem proving—to automatically extract formal models from LLM-generated Java code and iteratively refine it. Forge establishes a fully automated feedback loop that requires no manual intervention, successfully producing verifiable evidence aligned with industry certification requirements and thereby advancing the certifiability of AI-generated code in safety-critical domains.

This work addresses the challenge that large language models (LLMs) often introduce semantic or logical errors when generating hardware RTL code, failing to meet the stringent reliability requirements of chip design. To overcome this limitation, the paper proposes a novel hardware generation framework that integrates LLMs with formal methods, uniquely combining LLM-driven iterative refinement with formal verification. The approach leverages predefined transformation rules to guide the LLM in progressively refining high-level specifications into RTL code that is formally verifiable for correctness. This integration enhances both the interpretability and reliability of the code generation process. Experimental results demonstrate that the method is not only effective but also efficient in producing correct RTL implementations, thereby offering a promising pathway toward trustworthy LLM-assisted hardware design.

This work addresses critical challenges in safety-critical rule-based systems—namely poor scalability, fragility, and goal mis-specification—which often lead to reward hacking and failures in formal verification. To overcome these limitations, the authors propose a neuro-symbolic causal framework that integrates first-order logic abductive trees, structural causal models, and deep reinforcement learning within a MAPE-K control loop. A novel meta-layer architecture enables the automatic synthesis and formal verification of rules from natural language objectives. This meta-layer comprises a goal/rule synthesizer and a rule verification engine, which iteratively generate necessary and sufficient causal rule sets grounded in legal and safety principles provided by human experts. Evaluated in an autonomous driving scenario, the approach successfully derives a minimal yet complete rule set, formally encoded as logical constraints, demonstrating its modularity, traceability, and practical applicability.

This work addresses the semantic gap between natural language specifications and RTL designs, which often leads to SystemVerilog assertions containing syntactic errors or semantic inaccuracies that hinder formal verification. To bridge this gap, the authors propose a knowledge graph–based multi-agent collaborative framework that unifies specifications, RTL code, and verification feedback into a structured intermediate representation for the first time. This enables traceable, design-anchored contextual modeling and supports a closed-loop assertion refinement process through a triple iterative optimization mechanism—comprising syntax repair, counterexample-guided correction, and coverage-driven enhancement. Evaluated on seven benchmark designs, the generated assertions are all compilable with low syntax-repair overhead and achieve formal verification coverage ranging from 78.5% to 99.4%.

This work addresses the challenge of verification failures in loop invariant synthesis caused by local reasoning errors in large language models (LLMs). To this end, the authors propose LORIS, a novel framework that integrates formal verification of natural-language reasoning steps with feedback-driven iterative refinement. LORIS automatically translates LLM-generated natural language invariants into first-order logic and employs formal verification to detect logical inconsistencies, which are then used to generate targeted feedback for guiding the model to correct its reasoning trajectory. Experimental results demonstrate that LORIS achieves a 93.1% success rate on a benchmark of 460 C programs and exhibits strong robustness on 50 challenging programs involving nonlinear properties, substantially enhancing the reliability of LLM-based reasoning in program verification.

This work addresses the limitations of existing approaches to automatic SystemVerilog Assertion (SVA) generation—namely, erroneous signal references, missing temporal constraints, and the absence of formal correctness guarantees—by introducing ProofLoop, a tool-augmented ReAct agent that integrates a formal verification solver into the large language model reasoning loop. ProofLoop employs a two-stage pipeline: it first retrieves design context using EDA tools and an AST-based vector database, then iteratively refines assertions through structural queries in JasperGold and multi-round feedback from formal verification. Evaluated on the FVEval Design2SVA benchmark, ProofLoop achieves 93.7% syntactic correctness and 82.0% functional correctness. Ablation studies confirm that each component contributes significantly and orthogonally to overall performance.