design hil cps testbed

To address the dual challenges of ensuring power system reliability and robustness under sudden disturbances, and enabling machine learning models to simultaneously satisfy high-fidelity physics constraints and real-time deployment requirements, this paper proposes SafePowerGraph-HIL—a novel hardware-in-the-loop (HIL) framework. It integrates Hypersim real-time electromagnetic transient simulation, SCADA communication infrastructure, and AWS cloud services into a unified end-to-end closed-loop validation pipeline, enabling heterogeneous graph neural networks (HGNNs) for grid state estimation and dynamic analysis. The framework uniquely bridges high-fidelity physical simulation, streaming operational data, and deep learning model co-optimization—significantly narrowing the performance gap between simulation and field deployment. Experimental results demonstrate that the HGNN achieves sub-1.2% average prediction error across diverse operating conditions, improves robustness by 40%, and maintains real-time feasibility in edge–cloud collaborative environments.

In industrial cyber-physical systems (ICPS) research, demonstration objectives are often ill-defined, and technical feasibility assessment is frequently decoupled from outcome validation. Method: This paper proposes a five-level demonstration framework grounded in Maslow’s hierarchy of needs, systematically mapping demonstration goals to concrete research tasks and industrial use cases. It explicitly links work packages, verification metrics, and real-world scenarios, overcoming the vagueness and low operationality inherent in conventional Technology Readiness Level (TRL) frameworks. The approach integrates requirements engineering, modeling of software-intensive systems, and hierarchical framework design to support cross-phase requirements evolution analysis. Contribution/Results: Applied in two ICPS research projects, the framework effectively identified demonstration misalignments, refined requirement specifications, and significantly enhanced the precision, consistency, and rigor of feasibility assessment and project planning.

Industrial Control Systems (ICS) face escalating cyber threats due to increased connectivity, yet conventional honeypots—relying on firmware reverse engineering and expert-crafted rules—struggle to efficiently and realistically emulate multi-vendor protocols and PLC control logic. To address this, we propose the first large language model (LLM)-based, dynamically configurable ICS honeypot framework, leveraging LLaMA-3 and Qwen. Our approach integrates protocol semantic parsing, prompt-engineered control logic generation, and finite-state machine modeling to enable zero-shot, vendor-agnostic automation of both protocol and control behavior simulation. Evaluated across seven industrial protocols and twelve representative control scenarios, our framework achieves 98.2% session-level interaction fidelity, improves attack traffic capture rate by 3.8×, and reduces configuration time from hours to seconds—effectively overcoming the core bottlenecks of high manual effort and poor generalizability in ICS honeypot deployment.

Software engineers face significant challenges—including difficulty in modeling, lengthy prototyping cycles, and high verification costs—when developing control algorithms for complex dynamic systems such as communication networks. To address these issues, we propose GIPS, the first model-driven engineering framework that tightly integrates graph-structured integer linear programming (ILP) modeling with automated code generation. Using the domain-specific language GIPSL, users declaratively specify constraints and optimization objectives; GIPS then automatically generates functionally complete, executable Java graph-optimization components. This enables end-to-end rapid prototyping—from high-level specifications to runtime deployment. We validate GIPS on a tree-structured peer-to-peer topology control scenario, demonstrating its correctness, efficiency, and scalability. The full implementation—including source code and a ready-to-run virtual machine demonstration environment—is open-sourced, confirming its practical deployability and engineering utility.

To address the challenges of heterogeneity, fragmented resources, and inefficient collaboration in embedded-system virtual-prototype simulation tools, this paper proposes SUNRISE—a scalable infrastructure for distributed simulation. SUNRISE introduces the Simulation Adapter Abstraction Layer (SAAL), a novel abstraction enabling plug-and-play integration of seven major commercial and open-source simulators. It leverages lightweight containerization (Docker/Kubernetes) and a RESTful microservice architecture to dynamically orchestrate simulation tasks across decentralized computing resources. An open API gateway is designed to facilitate cross-organizational collaboration. Experimental evaluation demonstrates that SUNRISE reduces simulation-task deployment latency by 62%, improves cross-organizational collaboration efficiency by 3×, and achieves a 99.8% API call success rate.

This work addresses the validation gap between simulation and real-world deployment of autonomous driving algorithms, particularly the lack of efficient, high-fidelity testing platforms for safety-critical scenarios. To bridge this gap, the authors propose a mixed-reality hardware-in-the-loop testing framework that seamlessly integrates physical mobile robots with high-fidelity virtual environments, enabling multimodal sensing, vehicle-to-everything (V2X) communication, and large-scale multi-agent collaboration. A key innovation is the coexistence of physical and virtual agents within a unified architecture, coupled with an online learning controller based on control barrier functions (CBFs) that establishes an integrated perception-planning-control safety assurance mechanism. Experimental results demonstrate that the platform significantly enhances the reliability and efficiency of sim-to-real transfer and validates its effectiveness across diverse safety-critical scenarios.

This study addresses the common disconnect between SysML models and physical implementations in traditional model-based systems engineering, where models are often abandoned during hardware verification. To bridge this gap, the authors propose a novel bidirectional communication architecture that enables direct, real-time message exchange between executable SysML models and physical hardware—without requiring intermediate translation or co-simulation platforms. By integrating an embedded C++ SysML-side server into IBM Rhapsody and coupling it with a Raspberry Pi hardware interface, the approach embeds SysML statecharts directly into the hardware-in-the-loop verification loop. Validation on a logic gate case study demonstrates perfect output consistency between the SysML model and physical hardware, as confirmed by Karnaugh map comparison. This result substantiates the feasibility of model-driven hardware verification, significantly shortening the digital thread and enhancing model reuse throughout the development lifecycle.

This work proposes a novel approach to black-box testing of Functional Mock-up Units (FMUs) by integrating large language models (LLMs) with a human-in-the-loop mechanism. Addressing the inefficiency and poor interpretability of traditional FMU-based dynamic simulation testing—which relies on manually crafted scenarios—the method automatically generates structured Given-When-Then test objectives from FMU interface and functional specifications, and constructs complete test plans comprising input sequences and assertion oracles. Upon simulation execution, the framework produces visualizable logs and statistical evaluation metrics. The approach significantly enhances test design efficiency and result interpretability, facilitates test asset reuse, and demonstrates effectiveness on a lubricating oil cooling system by autonomously generating executable test scenarios and delivering objective-level pass-rate analysis.

Constrained by spatial limitations and sensor functionality in real-world testing environments, underwater vehicles face significant challenges in validation. To address this, this study develops a collaborative Hardware-in-the-Loop (HIL) and Software-in-the-Loop (SIL) simulation test framework tailored for the CougUV autonomous underwater vehicle (AUV). The key contribution is the first deep integration of the high-fidelity underwater simulator HoloOcean 2.0 with ROS 2, enabling bidirectional interaction between real-sensor-data-driven simulation and closed-loop control commands. This integration substantially enhances the fidelity, reproducibility, and scalability of virtual testing. Experimental evaluation demonstrates strong consistency between simulated and at-sea test results—position error < 0.15 m and attitude deviation < 2.1°—validating the framework’s effectiveness and engineering reliability for closed-loop verification of control, navigation, and perception algorithms.