event-based timestamping

Existing software simulation of Time-Sensitive Networking (TSN) suffers from insufficient accuracy in measuring bridge delay and jitter, undermining the fidelity and reproducibility of TSN emulation. Method: This paper introduces the first systematic timestamping methodology for TSN simulation on Linux/Mininet, rigorously evaluating four timestamping mechanisms—including SO_TIMESTAMPING—under TSN traffic shaped by Credit-Based Shaping (CBS) and Asynchronous Traffic Shaping (ATS). Leveraging configurable Mininet topologies, the approach integrates scheduling solution generation, deployment validation, and cross-platform optimization—supporting both Intel Time-Coordinated Computing (TCC)-enabled and -disabled modes on industrial PCs and workstations. Contribution/Results: The framework achieves sub-microsecond bridge delay characterization and, for the first time, experimentally validates end-to-end deterministic guarantees on real hardware. It overcomes critical bottlenecks in clock synchronization precision and scheduling fidelity, significantly enhancing the trustworthiness and reproducibility of TSN simulation.

This study addresses the reliability degradation of event timelines in digital forensics due to user-initiated timestamp tampering on live systems. Conducting a qualitative user study with advanced students, we employ trace analysis, timestamp dependency modeling, and second-order trace resolution path induction to systematically uncover the “cognitive–technical” coupling barriers inherent in timestamp manipulation—a first-of-its-kind investigation. We propose a reliability assessment framework grounded in trace knowledge depth and modification feasibility, identifying core determinants of tampering success—including temporal trace recognition capability and kernel- or filesystem-level constraints. The framework provides empirically validated criteria for time-based evidentiary trustworthiness grading, enabling more accurate and robust forensic timeline reconstruction. Results demonstrate significant improvements in both precision and resilience of event reassembly under adversarial timestamp modification scenarios.

In distributed systems, clock asynchrony impedes fair and deterministic total ordering of events. Method: This paper proposes a probabilistic event serialization framework that replaces the deterministic “happened-before” relation with a novel “likely-happened-before” probabilistic ordering. It models per-node clock skews as time-varying probability distributions and performs Bayesian comparison of noisy timestamps to infer the most probable causal order. Crucially, it requires no strong clock synchronization assumptions and operates online. Contribution/Results: The approach enables fine-grained, statistically fair total order generation without global consensus or physical clock alignment. Experiments demonstrate accurate estimation of relative occurrence probabilities between events. The method provides a provably sound, scalable foundation—both theoretically and empirically—for achieving system-wide fairness in asynchronous environments.

This work addresses the challenge of fair event ordering in distributed systems, where clock synchronization errors complicate deterministic sequencing. The authors propose Tommy, a novel sequencer that, for the first time, integrates social choice theory into event ordering. By modeling the statistical characteristics of clock synchronization errors, Tommy probabilistically compares noisy timestamps and reformulates the ordering task as a social choice problem, yielding a partially ordered sequence. Rather than attempting to eliminate clock inaccuracies, Tommy explicitly tolerates them, effectively handling the non-transitivity inherent in probabilistic comparisons. This approach ensures fairness in a probabilistic sense while significantly outperforming baseline methods based on Spanner’s TrueTime.

High-precision online estimation algorithms for robotics are highly sensitive to sensor timestamp accuracy; however, existing synchronization solutions struggle to simultaneously achieve real-time operation, low cost, and high temporal precision. To address this, we propose a real-time, trigger-based time synchronization system built on commodity hardware. Our approach employs a hardware-triggered mechanism to jointly schedule heterogeneous sensors operating at different frequencies, and integrates an enhanced clock synchronization protocol with nanosecond-resolution timestamping to ensure precise coordination between sensors and the onboard computer. Crucially, the system eliminates reliance on expensive dedicated timing hardware, thereby substantially mitigating the impact of timing errors on online estimation. Experimental evaluation on a physical robot platform demonstrates sub-microsecond synchronization accuracy, along with significant improvements in both estimation robustness and real-time performance.

This study addresses the lack of empirical evaluation of NVIDIA ConnectX NICs’ high-precision scheduling and hardware timestamping capabilities under real-world conditions, which has hindered clear assessment of their suitability for stringent timing requirements in deterministic networks such as 5G fronthaul and Time-Sensitive Networking (TSN). Leveraging an FPGA-based nanosecond-precision measurement platform, this work presents the first public quantification of the hardware timestamp accuracy and Accurate Scheduling transmission timing performance of the ConnectX-7 NIC. Experimental results show that cross-device timestamp deviations are approximately ±7–8 ns, and 99% of scheduled frames are transmitted within ±900 ns of their target time, with rare outliers reaching up to 5 μs. These findings indicate that the NIC meets the tens-of-microseconds timing demands of 5G fronthaul but falls short of the sub-microsecond precision required by TSN, thereby filling a critical gap in industrial empirical understanding of this hardware’s deterministic networking capabilities.

Network congestion induces delay jitter in time synchronization packets, significantly degrading the clock synchronization accuracy of protocols such as NTP and PTP. This work proposes a lightweight congestion marking mechanism that leverages existing unused fields in IP, PTP, or NTP headers to tag synchronization packets experiencing queuing delays on programmable switches (Tofino platform), without requiring deep packet inspection or protocol modifications, thereby preserving backward compatibility. At the receiver, statistical filtering strategies—combining minimum RTT and median delay estimates—effectively discard congestion-affected packets. Experimental results demonstrate that the proposed approach improves synchronization accuracy by over 80% in single-hop scenarios and reduces clock offset estimation error by 30%–80% in multi-hop environments, achieving up to a 90% performance gain over conventional filtering methods.

This work addresses the vulnerability of time-integrity–based anomaly detection in energy Internet-of-Things (IoT) systems to attacks such as clock drift, time synchronization tampering, and Y2K38 overflow, which compromise the reliability of trusted timestamps. To counter this, the authors propose STGAT, a novel framework that integrates clock dynamics awareness into a spatiotemporal graph neural network. STGAT jointly models individual device time distortions and collective temporal consistency through drift-aware temporal embeddings, temporal self-attention, and graph attention mechanisms. Furthermore, it employs curvature regularization to geometrically separate normal and anomalous behaviors in the latent space. Experimental results on energy IoT datasets with controlled perturbations demonstrate that STGAT achieves a detection accuracy of 95.7%, significantly outperforming baseline methods (Cohen’s d > 1.8, p < 0.001), while reducing detection latency by 26%—equivalent to only 2.3 time steps.