hardware timestamping

Existing software simulation of Time-Sensitive Networking (TSN) suffers from insufficient accuracy in measuring bridge delay and jitter, undermining the fidelity and reproducibility of TSN emulation. Method: This paper introduces the first systematic timestamping methodology for TSN simulation on Linux/Mininet, rigorously evaluating four timestamping mechanisms—including SO_TIMESTAMPING—under TSN traffic shaped by Credit-Based Shaping (CBS) and Asynchronous Traffic Shaping (ATS). Leveraging configurable Mininet topologies, the approach integrates scheduling solution generation, deployment validation, and cross-platform optimization—supporting both Intel Time-Coordinated Computing (TCC)-enabled and -disabled modes on industrial PCs and workstations. Contribution/Results: The framework achieves sub-microsecond bridge delay characterization and, for the first time, experimentally validates end-to-end deterministic guarantees on real hardware. It overcomes critical bottlenecks in clock synchronization precision and scheduling fidelity, significantly enhancing the trustworthiness and reproducibility of TSN simulation.

High-precision online estimation algorithms for robotics are highly sensitive to sensor timestamp accuracy; however, existing synchronization solutions struggle to simultaneously achieve real-time operation, low cost, and high temporal precision. To address this, we propose a real-time, trigger-based time synchronization system built on commodity hardware. Our approach employs a hardware-triggered mechanism to jointly schedule heterogeneous sensors operating at different frequencies, and integrates an enhanced clock synchronization protocol with nanosecond-resolution timestamping to ensure precise coordination between sensors and the onboard computer. Crucially, the system eliminates reliance on expensive dedicated timing hardware, thereby substantially mitigating the impact of timing errors on online estimation. Experimental evaluation on a physical robot platform demonstrates sub-microsecond synchronization accuracy, along with significant improvements in both estimation robustness and real-time performance.

This work addresses the inefficiencies and semantic inconsistencies arising from separately implementing driver and monitor programs in traditional hardware module testing. To overcome this, the authors propose a domain-specific language (DSL) tailored to hardware communication protocols, which enables the unified specification of both driver and monitor logic through an imperative syntax, thereby ensuring their semantic consistency for the first time. Building upon this DSL, they develop a prototype tool that leverages waveform parsing and transaction-level trace inference techniques to accurately reconstruct protocol-compliant transaction sequences from raw signal waveforms. Experimental results demonstrate that the approach significantly improves development efficiency, with further validation planned on real-world interconnect protocols such as Wishbone and AXI-Stream.

Network congestion induces delay jitter in time synchronization packets, significantly degrading the clock synchronization accuracy of protocols such as NTP and PTP. This work proposes a lightweight congestion marking mechanism that leverages existing unused fields in IP, PTP, or NTP headers to tag synchronization packets experiencing queuing delays on programmable switches (Tofino platform), without requiring deep packet inspection or protocol modifications, thereby preserving backward compatibility. At the receiver, statistical filtering strategies—combining minimum RTT and median delay estimates—effectively discard congestion-affected packets. Experimental results demonstrate that the proposed approach improves synchronization accuracy by over 80% in single-hop scenarios and reduces clock offset estimation error by 30%–80% in multi-hop environments, achieving up to a 90% performance gain over conventional filtering methods.

This study addresses the lack of empirical evaluation of NVIDIA ConnectX NICs’ high-precision scheduling and hardware timestamping capabilities under real-world conditions, which has hindered clear assessment of their suitability for stringent timing requirements in deterministic networks such as 5G fronthaul and Time-Sensitive Networking (TSN). Leveraging an FPGA-based nanosecond-precision measurement platform, this work presents the first public quantification of the hardware timestamp accuracy and Accurate Scheduling transmission timing performance of the ConnectX-7 NIC. Experimental results show that cross-device timestamp deviations are approximately ±7–8 ns, and 99% of scheduled frames are transmitted within ±900 ns of their target time, with rare outliers reaching up to 5 μs. These findings indicate that the NIC meets the tens-of-microseconds timing demands of 5G fronthaul but falls short of the sub-microsecond precision required by TSN, thereby filling a critical gap in industrial empirical understanding of this hardware’s deterministic networking capabilities.

This work addresses the challenge of detecting architectural drift—discrepancies between design-time architecture and runtime behavior—in long-lived embedded firmware. The authors propose a practical, hardware-assisted detection approach that captures runtime execution traces, abstracts them into inter-component message interaction sequences, and performs deterministic comparison against design-phase UML sequence diagrams to precisely identify confirmed, missing, extraneous, or inverted behavioral deviations. To facilitate expert review, the method further leverages a constrained large language model to generate human-readable explanatory reports. Integrating runtime trace analysis, deterministic architectural conformance checking, and constraint-guided LLM-based explanation generation for the first time, the approach demonstrates high agreement with expert annotations across 26 industrial cases, substantially reducing manual analysis effort while effectively supporting ISO 26262 safety documentation requirements.

This study addresses the significant barriers to security research on low-cost consumer drones, whose firmware is hindered by a lack of public documentation and difficulty in acquisition. Focusing on three Holy Stone drone models, the work proposes a non-invasive fixture-based contact method that avoids chip desoldering and leverages low-cost interfaces—including SPI flash reading, SWD/JTAG debugging, and UART log capture—to establish a three-tier verification framework. This framework integrates sliding-window Shannon entropy analysis, Binwalk structural signatures, and EMBA static analysis to ensure firmware integrity and authenticity. The approach successfully extracted and validated multiple genuine firmware images, revealing outdated library components containing known CVE vulnerabilities and a notable absence of binary hardening. These findings provide a reproducible baseline methodology and reliable data foundation for future firmware re-hosting and systematic security assessments.

This work addresses the inefficiencies in hardware-software co-integration of modern accelerators, which stem from architectural complexity, deep memory hierarchies, and heavy reliance on production firmware. Traditional FPGA-based simulation workflows suffer from slow debugging cycles and prolonged iteration times. To overcome these limitations, we present the first framework enabling cycle-accurate co-verification of production firmware with RTL or gate-level hardware models within standard simulators such as VCS, Xcelium, and Vivado Xsim. By compiling firmware to x86 and bridging it with the hardware emulation subsystem—augmented with a randomized memory bridge—the framework supports second-scale debugging, register-level protocol validation, off-chip dataflow analysis, and memory congestion emulation. Evaluated on accelerators including systolic arrays and CGRAs, our approach achieves up to 50× faster debugging and significantly enhances parallel development efficiency and functional verification reliability for heterogeneous computing platforms.