hardware backend integration

This work addresses the persistent challenge of inconsistent development and execution environments faced by researchers operating across heterogeneous computing platforms—ranging from laptops and workstations to supercomputers and cloud infrastructures. To overcome this, the authors propose a modular and portable software ecosystem featuring a unified command-line interface that enables seamless orchestration and execution of scientific workflows. The system ensures cross-platform consistency, reproducibility, and scalability, thereby streamlining computational research across diverse hardware configurations. Its practical efficacy has been demonstrated through successful integration into the plan4res project under the European Union’s Horizon 2020 initiative, where it effectively supported complex, large-scale scientific workflows in varied computing environments.

This work addresses the inefficiencies and semantic inconsistencies arising from separately implementing driver and monitor programs in traditional hardware module testing. To overcome this, the authors propose a domain-specific language (DSL) tailored to hardware communication protocols, which enables the unified specification of both driver and monitor logic through an imperative syntax, thereby ensuring their semantic consistency for the first time. Building upon this DSL, they develop a prototype tool that leverages waveform parsing and transaction-level trace inference techniques to accurately reconstruct protocol-compliant transaction sequences from raw signal waveforms. Experimental results demonstrate that the approach significantly improves development efficiency, with further validation planned on real-world interconnect protocols such as Wishbone and AXI-Stream.

为解决固件重宿中外围设备建模不准确的问题，提出反应式外围建模（RPM）方法，通过事件-条件-动作语义忠实再现复杂外设行为。

Heterogeneous hardware environments exhibit uneven resource distribution, rendering conventional lock mechanisms performance bottlenecks; existing solutions typically target single hardware types and fail to coordinate heterogeneous resources effectively. This paper introduces Modular Lock Decomposition—a novel paradigm that decouples lock functionality into independent, deployable modules (e.g., acquisition, waiting, wakeup) and dynamically assigns each module to appropriate hardware components (e.g., CPU cores, GPUs, FPGAs, cache levels) based on their architectural characteristics, enabling fine-grained, cross-architecture resource adaptation. To our knowledge, this is the first systematic shift in lock design from monolithic structures to hardware-aware modular architectures. Experimental evaluation under typical concurrent workloads demonstrates an average 42% reduction in lock contention latency and a 1.8× throughput improvement, significantly enhancing lock scalability and heterogeneous resource utilization.

Existing hardware and software defenses against fine-grained memory-access vulnerabilities (e.g., out-of-bounds access, ROP attacks) stemming from third-party code struggle to simultaneously achieve strong security, low overhead, and broad portability. Method: This paper proposes a dynamic in-process address-space isolation mechanism that enables multi-privilege, programmable security domains within a single virtual address space—ensuring end-to-end protection for both data and control flows while supporting secure system calls. It introduces the first “dynamically code-segment-driven” isolation architecture, overcoming limitations of static partitioning in granularity, performance cost, and compatibility. The design integrates a custom secure processor microarchitecture (FPGA prototype), QEMU-based simulation, compiler-assisted tagging, and runtime monitoring. Results: Evaluation demonstrates robust resilience against representative memory corruption attacks, with average hardware overhead under 8%—significantly outperforming pure-software approaches—while preserving binary compatibility.

本文通过引入Griotte和Griotte OS，利用形式化方法验证了CHERIoT基于能力的隔离机制的有效性和安全性。

This work addresses the challenges in edge and embedded application development—namely, heterogeneous software stacks, multi-language runtimes, and difficult debugging—which lead to rigid deployment workflows and complex fault diagnosis. To overcome these limitations, the paper proposes a novel architecture enabling unified end-edge-cloud development. Its core components include a single programming language, a retargetable runtime system, a local recording and replay mechanism for distributed events, and a cross-platform deployment framework. This design breaks down traditional debugging barriers in edge–cloud collaborative development, facilitating seamless scalability, consistent testing, and flexible deployment across heterogeneous environments. Evaluation of the prototype system demonstrates that the proposed approach significantly simplifies deployment procedures and enhances fault diagnosis efficiency.

论文提出了一种针对资源受限嵌入式系统的云端事务编排框架，通过迁移状态机和微服务编排到云端，并采用双握手协议，减少了客户端开销并提高了交易性能。

This work addresses the inefficiency of manual VCD file analysis in hardware security research, where practitioners often laboriously inspect waveform traces to identify software-hardware interface vulnerabilities. To overcome this bottleneck, the paper introduces RTL-Arrow, a novel framework that automatically transforms VCD execution traces—generated from hardware simulation—into cloud-ready, structured data frames compatible with modern data science workflows. RTL-Arrow integrates VCD parsing, structured data frame construction, and cloud-native format encapsulation, complemented by an automated compilation pipeline that produces a high-performance toolchain. Released as an open-source library, RTL-Arrow substantially lowers the barrier to hardware-software co-verification, significantly enhancing the efficiency and scalability of cross-layer vulnerability detection and analysis.

Existing WebAssembly-based serverless platforms are typically tied to specific execution engines and support only stateless applications, making them ill-suited for deploying stateful applications in edge computing environments under heterogeneous hardware and workload constraints. To address this limitation, this work proposes WASP, a framework featuring a fully decoupled, plug-in architecture that enables flexible configuration of runtime environments, data storage, lifecycle management, and caching policies—without requiring modifications to application code. WASP is the first to enable portability of stateful serverless applications across the edge-to-cloud continuum, overcoming the hard-coded runtime and state management restrictions of current platforms. Experimental results demonstrate that WASP incurs negligible runtime overhead while significantly tuning memory usage and latency, thereby effectively adapting to heterogeneous edge–cloud scenarios.