low-power circuit design

In nanoscale modular electronics (ME/NE) design automation, a fundamental trade-off exists between manufacturing time and bus length during component placement and routing. This work presents the first systematic exploration of this time–performance Pareto space, introducing an adaptive hierarchical algorithmic framework that integrates partitioning, floorplanning, stochasticity-aware component placement, and precise wire-printing–guided routing. The method explicitly accounts for the inherent randomness in micro/nanoscale deposition processes and supports dynamic reweighting of optimization objectives. Experimental results demonstrate that, with only a 21% increase in total wirelength, end-to-end fabrication time improves by up to 108×; alternatively, circuit performance can be prioritized without compromising manufacturability. This approach significantly enhances flexibility, scalability, and process–design co-optimization for heterogeneous nanocircuit synthesis.

This work addresses the fragmented nature of existing neural network processor design across training, mapping, and manufacturing stages, which hinders joint optimization of performance, cost, and yield under uncertainty. The authors propose a unified framework grounded in monotonic co-design theory, decoupling training, mapping, manufacturing, and resource allocation through a functional-resource interface to enable both independent optimization and global coordination. A key innovation is the explicit introduction of “confidence” as an optimizable resource within the design flow, allowing uncertainty to be formally modeled while guaranteeing that local improvements automatically advance the global Pareto front. The efficacy of the approach is demonstrated through three case studies: reproducing Pareto-optimal solutions in heterogeneous scenarios, validating confidence as a continuously tunable parameter, and achieving global performance gains without requiring hardware reconfiguration.

To address the inefficiency of general-purpose microprocessors in machine learning (ML) tasks under stringent area and power constraints inherent to printed electronics, this paper proposes a ML-oriented customized printed microprocessor design methodology. The approach involves eliminating redundant logic, deeply integrating reconfigurable SIMD multiply-accumulate (MAC) units, and adapting the Zero-Riscy open-source core to enable algorithm-architecture co-optimization. Its key contribution is the first printed-electronics-compatible ML customization paradigm, featuring a configurable SIMD accelerator supporting four precision levels. Silicon validation demonstrates 22.2% area reduction, 23.6% power savings, and 33.8% speedup over the baseline design, while maintaining lossless inference accuracy across six ML models. Compared to state-of-the-art printed processors, it achieves significant performance gains under controllable accuracy degradation.

As technology scales down and supply voltages decrease, soft error probability (SEP) in nanoscale circuits is increasingly affected by the coupled effects of process variation (PV) and aging—yet existing methods either neglect this coupling or rely on computationally expensive Monte Carlo simulations, hindering scalability for large-scale reliability optimization. This paper proposes the first analytical framework jointly modeling PV and aging, introducing an enhanced electrical masking model integrated with a statistical SEP computation methodology. Leveraging theoretical derivation validated by Monte Carlo simulation, the approach achieves high accuracy while significantly improving computational efficiency. Experimental results demonstrate a ~2.5% reduction in computational overhead compared to conventional Monte Carlo simulation, without sacrificing estimation accuracy. The framework thus provides an efficient, scalable foundation for reliability-driven design of large digital circuits.

This work addresses thermal–electrical performance degradation induced by process variations in 3.5D heterogeneous integration by introducing XRM-SSD V24/V7.0, a physics-aware predictive firmware scheduling layer that enables hardware–software co-optimization. Prior to tape-out, it dynamically regulates PowerVia voltage rails through a workload-density-driven thermal pre-hinting mechanism. For the first time, forward-looking thermal hints are integrated with multi-die interconnect architectures and extended to multi-tile systems, establishing an N×N thermal coupling matrix and a bipolar core model. Leveraging electro-thermal co-simulation, Monte Carlo process variation analysis, and a large-scale LLM inference workload dataset (90,000 timesteps), the approach achieves a thermal load correlation coefficient of R² = 0.9911, reduces compensated CPO spectral drift to below 0.36 nm, limits HBM leakage current to under 1 MB/hr, and is projected to unlock 20–30% additional compute capacity while reducing EDA guardbands by 65–68%.

This work addresses the high-dimensional, complex trade-offs inherent in analog-mixed signal circuit sizing, a task where existing methods struggle to effectively leverage circuit schematics and lack interpretability. The authors propose a multi-agent collaborative optimization framework integrating vision-language models, which employs an Image2Net module to structurally parse circuit diagrams, JSON-based semantic descriptions, an interpretable trust-region Bayesian optimizer (ExTuRBO), and dual-granularity sensitivity analysis to enable reasoning-driven sizing and collaborative warm-starting. Evaluated across technology nodes from 180 nm to 45 nm, the approach achieves 100% success in designing complementary-input and class-AB output-stage amplifiers within under 43 minutes total runtime, striking a favorable balance between power consumption and performance while significantly advancing automation and industrial interpretability.

At advanced technology nodes, the tight coupling between layout and electrical performance in analog circuits poses significant challenges for automated placement. This work proposes a row-height-quantized cell-based layout synthesis methodology, systematically introducing row-height quantization into analog circuit design for the first time. By optimizing row-height structures, modeling layout constraints, and enabling automatic mapping of analog modules onto quantized rows, the approach effectively bridges the performance gap between schematic and post-layout stages. Experimental results across multiple test cases demonstrate that the method achieves performance close to manual custom design, reducing the schematic-to-post-layout performance deviation by up to 68.5% and decreasing area overhead by as much as 24.1%.

This work addresses the long-term inference accuracy degradation in 65 nm single-poly floating-gate analog in-memory computing chips caused by diminished charge retention. To mitigate this issue, the study introduces, for the first time, a circuit-algorithm co-compensation strategy that integrates circuit-level compensation—guided by statistical modeling of retention loss—with batch normalization recalibration. Evaluated on VGG-10/CIFAR-10 and WideResNet-28-10/CIFAR-100 models, the proposed approach restores inference accuracy to within 2–4% of the baseline even after 60 days of programming. This significant recovery demonstrates a marked enhancement in the long-term reliability and practicality of non-volatile analog in-memory computing systems.

This work addresses the significant challenge posed by bias temperature instability (BTI) and random process–voltage (PV) variations to digital circuit reliability in deep-nanometer CMOS technologies, where conventional analysis methods suffer from high computational cost and poor scalability. To overcome these limitations, the paper proposes a novel gate-level delay distribution prediction framework that uniquely integrates random forest regression with Bayesian optimization. By leveraging offline training on Monte Carlo simulation data—bypassing time-consuming atomic parameter extraction—and employing Bayesian optimization for automated hyperparameter tuning, the approach achieves substantially improved accuracy and efficiency. Experimental validation on ISCAS85 benchmark circuits demonstrates a 94.54% reduction in analysis time compared to the state-of-the-art method, with an average prediction error of only 1.63%.

This work addresses the legalization of Adiabatic Quantum-Flux-Parametron (AQFP) circuits, which requires inserting buffers and splitters due to gate-level pipelining and explicit fanout constraints. Conventional approaches suffer from a misalignment between optimization objectives and physical design costs. To bridge this gap, we formulate the problem for the first time as minimizing the circuit width–depth product—a metric more closely correlated with actual layout area—and prove it to be NP-complete. We propose a placement-aware heuristic algorithm that jointly optimizes legalization and physical constraints. Experimental results on benchmark circuits demonstrate that our method reduces post-placement area by 30% on average (up to 61%) with only a ~3% increase in Josephson junction count, establishing a new paradigm for AQFP physical design.