timing closure

This study addresses the fundamental differences and challenges in timing closure between FPGAs and ASICs. To tackle timing behavior divergence arising from their architectural heterogeneity, we propose the first cross-platform unified timing analysis framework, integrating static timing analysis, process-node-aware comparison, and silicon measurement validation. Using a comparative case study of Xilinx Kintex UltraScale+ FPGAs and 7 nm ASICs, we quantitatively characterize their timing performance boundaries: the ASIC achieves 45 ps setup and 35 ps hold times, while the FPGA attains 180 ps setup and 120 ps hold times—demonstrating substantial improvements in high-precision timing control for modern high-end FPGAs. The framework systematically elucidates the architecture–timing mapping relationship and enables performance- and programmability-aware co-design decisions in heterogeneous computing platforms. It provides both theoretical foundations and practical guidelines for high-performance reconfigurable systems.

This paper addresses the automated layout design problem for stripboard (perfboard) circuits. We propose a declarative synthesis and multi-objective optimization approach based on Answer Set Programming (ASP). The problem is modeled holistically to enforce electrical connectivity, geometric constraints, and minimization of wire crossings. A two-stage solving strategy is adopted: first ensuring layout feasibility, then jointly optimizing board area and the number of component jumper connections (i.e., through-hole interconnections). Unlike traditional heuristic methods, our declarative formulation naturally encodes complex domain constraints, yielding higher-quality and more manufacturable solutions. Experimental evaluation across circuits of varying complexity demonstrates that our method consistently produces compact, low-crossing, and solder-friendly layouts—achieving an average 18.7% reduction in board area and a 32.4% decrease in jumper count. The approach is particularly suitable for electronic prototyping and educational applications.

This study addresses the challenge of systematically comparing timing behavior of RISC-V processors across heterogeneous technology platforms—specifically, 20 nm FPGAs versus 7 nm FinFET ASICs. We propose a microarchitectural-level, cross-platform timing attribution methodology that integrates static timing analysis (STA), PVT-corner statistical characterization, and pipeline-stage decoupled modeling. Our approach establishes a three-component decomposition framework—logic, routing, and clock—and precisely localizes timing-critical transitions to individual pipeline stages. For the first time, we reveal that FPGA timing is dominated by routing parasitics and topology sensitivity, yielding wide yet scattered timing margins; in contrast, ASIC timing is governed by combinational logic depth and PVT stability, resulting in narrow, concentrated margins. Quantitatively, we identify the EX→MEM stage transition as the common critical path across both platforms. Based on this insight, we formulate predictive, heterogeneity-aware design guidelines for timing convergence.

To address layout inefficiency, communication redundancy, unmeasurable power consumption, and limited scalability in Multi-Project Wafer (MPW) platforms for large-scale chip education and research, this paper proposes a high-density, low-cost, and scalable on-chip shared architecture. Methodologically: (1) an algorithm-driven automated floorplanning framework maximizes die area utilization; (2) a novel lightweight interconnect and resource-sharing mechanism leverages site-gap regions, eliminating redundant dedicated I/O and memory macros; (3) modular power-domain partitioning and on-die power monitoring enable per-project power characterization. Experimental results demonstrate up to 13× reduction in die area compared to conventional physically co-located MPW implementations, significantly improving resource utilization and project throughput—without requiring expertise in low-power ASIC design.

This work addresses the challenge that existing large language models struggle to simultaneously satisfy stringent geometric, routing, and electrical connectivity constraints in dense PCB layout design. To bridge this gap, we introduce OmniLayout, the first multimodal benchmark specifically tailored for PCB layout, which jointly models schematic diagrams and physical layouts. The benchmark encompasses four constraint-aware reasoning tasks designed to systematically evaluate model capabilities in geometric reasoning, routability, preservation of electrical functionality, and tool invocation. Integrating industrial-scale layout data, geometric constraint modeling, routing analysis, and circuit verification, our framework exposes critical limitations of current models—particularly their weak geometric reasoning, poor routing optimization, and insufficient functional consistency—thereby filling a crucial void in evaluating multimodal collaborative reasoning within electronic design automation.

This work addresses the limitations of existing FPGA placement tools, which rely on two-dimensional frameworks and struggle to effectively optimize the inter-layer timing and routing characteristics unique to 3D FPGAs. The paper presents the first complete placement flow specifically designed for 3D FPGAs, integrating partition-based initialization, adaptive cost scheduling, fine-grained delay modeling, and a 3D-aware simulated annealing move strategy to jointly optimize layer assignment and timing. Experimental results across four representative 3D architectures demonstrate that the proposed method reduces critical path delay by 2%–6% on average (up to 18%) and decreases total wirelength by 1%–5% on average (up to 10%), significantly improving both timing and routing quality.

This work addresses the ongoing challenge of automatically translating natural language specifications into editable printed circuit board (PCB) schematics for embedded and IoT development. It presents the first end-to-end approach that leverages tool-augmented large language model reasoning, integrating component library retrieval, datasheet knowledge extraction, execution validation, and structural-semantic verification to generate KiCad-compliant schematics. The system supports iterative refinement through an interactive web interface and achieves a pass@1 rate of 0.90 and a pass@5 rate of 1.00 across 20 embedded schematic generation tasks. This method efficiently produces high-quality initial drafts suitable for early-stage prototype review, substantially advancing the state of hardware design automation.

This work proposes a personalized prototyping platform for circuit development to address the limitations of traditional tutorial-based approaches, which rely on rigid, fixed-step instructions that fail to accommodate makers’ individualized building and debugging practices. Central to the platform is a circuit-aware enhanced breadboard integrated with hardware-in-the-loop reconfiguration, context-aware guidance algorithms, and in-situ interactive testing techniques. This integration enables, for the first time, nonlinear, real-time, hardware-context-driven guidance and circuit validation. A user study (N=12) demonstrates that the system effectively aligns with users’ unique construction and troubleshooting behaviors, significantly improving both prototyping efficiency and user experience.

This work addresses the limited reproducibility and comparability of machine learning research in electronic design automation (EDA), which stems from the absence of open, standardized datasets. To bridge this gap, the authors propose EDA-Schema-V2—the first standardized multimodal data schema encompassing the full EDA flow from logic synthesis to detailed routing. Leveraging open-source PDKs such as SkyWater 130nm and Nangate 45nm, along with the OpenROAD framework, they generate a large-scale open dataset comprising 7,776 design instances, over 275 million logic gates, and 36 million timing paths through systematic sweeps of process corners, clock periods, and placement parameters. The study defines twelve representative prediction tasks and establishes cross-stage predictability baselines, thereby providing a reproducible benchmark for ML-driven EDA research.

Congestion in VLSI placement is typically identifiable only after detailed routing, rendering conventional validation workflows time-consuming and costly. This work proposes VeriHGN, a novel framework that for the first time deeply integrates the logical connectivity of circuit netlists with physical placement grids into a unified, enhanced heterogeneous graph representation, overcoming the limitations of prior loosely coupled modeling approaches. Leveraging a heterogeneous graph neural network, the method achieves state-of-the-art performance on industrial benchmarks—including ISPD2015, CircuitNet-N14, and CircuitNet-N28—demonstrating superior accuracy and correlation in early-stage congestion prediction compared to existing techniques.