rtl design

Accelerator Design Language (ADL) compilers suffer from unpredictable hardware performance due to the semantic gap between high-level abstractions and low-level implementations, compounded by reliance on heuristic optimizations. This work introduces Petal, the first tool enabling cycle-accurate, interpretable performance analysis for Calyx-based accelerators. Petal bridges the abstraction gap via three key techniques: source-code instrumentation, RTL-simulation trace collection, and a novel reverse-mapping algorithm that associates low-level timing events in synthesized hardware with high-level control-flow constructs. Crucially, it abandons the “compiler-perfection” assumption, instead exposing how concrete compilation decisions impact end-to-end latency. Evaluated on multiple real-world accelerator designs, Petal identifies subtle, manually elusive bottlenecks—enabling targeted manual optimizations that reduce total execution cycles by up to 46.9% for one application.

Existing RISC-V ASIP frameworks suffer from weak hardware synthesis capability and poor compiler retargetability, hindering domain-specific performance gains. This paper proposes an MLIR-based hardware-software co-optimization framework: (1) a burst DMA engine is designed and integrated with high-level synthesis (HLS) optimizations to enhance automated hardware generation; (2) an e-graph–based retargetable compiler is developed, incorporating a novel matching engine to improve instruction selection efficiency and co-design flexibility. The framework unifies multi-level IR abstractions, enables automatic hardware synthesis, and supports semantic-aware pattern matching. Evaluated on real-world workloads—including point-cloud processing and large language model inference—the framework achieves up to 9.27× end-to-end speedup over state-of-the-art ASIP approaches, demonstrating significant improvements in both synthesis capability and compiler adaptability.

High-level synthesis (HLS) tools—such as Chisel and commercial HLS compilers—often produce circuits with inferior performance compared to hand-designed hardware in high-performance computing (HPC) accelerator design. Method: This paper proposes a hierarchical algorithmic decomposition and automated evaluation framework that abstracts mathematical kernels (e.g., Fourier transforms, matrix multiplication, QR decomposition) into reusable building blocks, uniformly implemented across multiple abstraction levels (RTL, Chisel, C++ HLS), and systematically benchmarked for resource utilization, timing, and operating frequency. Contribution/Results: The framework establishes the first cross-abstraction-level fair benchmarking methodology, enabling fine-grained identification of inefficiencies introduced by HLS compilers. Experimental evaluation demonstrates significantly improved accuracy and interpretability in pinpointing design bottlenecks, providing quantitative guidance for both HLS tool optimization and practical hardware design.

This work addresses the limitations of existing high-level synthesis (HLS) tools in balancing sequential semantics with fine-grained control over pipeline design, which hinders optimization of power, performance, and area (PPA). The paper proposes a novel HLS approach based on visibility control that preserves a sequential programming model while enabling precise manipulation of pipeline structures and hazard-handling mechanisms through a unified visibility abstraction. This framework encompasses strategies such as stall insertion, bypassing, speculative execution, delayed commit, and register renaming. Experimental results on a RISC-V core, histogram computation, and an AES accelerator demonstrate that the generated pipelines significantly outperform those from state-of-the-art sequential-semantics-preserving HLS tools, achieving PPA metrics close to hand-optimized RTL implementations and enabling efficient design space exploration.

Manual pragma configuration in high-level synthesis (HLS) suffers from low efficiency and an exponentially large search space. Method: This paper proposes the first nonlinear programming (NLP)-based automated pragma insertion framework, jointly optimizing loop-level pragmas—including pipelining, function unit replication, and data caching. It innovatively models discrete pragma configurations as continuous, differentiable variables and constructs analytical performance/resource models with theoretical lower-bound guarantees, solved globally via NLP. Integrated with pragma semantic analysis and the Merlin compiler, and augmented by design-space pruning, the framework explores billion-scale configurations within seconds to minutes. Contribution/Results: Experimental evaluation shows kernel performance approaching hand-tuned implementations, resource estimation error <8%, and latency lower-bound error ≤12%.

This work proposes Arch, an AI-native hardware description language that addresses the limitations of traditional HDLs, which lack native support for microarchitectural constructs, are prone to implicit errors such as clock domain crossings, and are poorly suited for reliable AI-based code generation. Arch is the first HDL to integrate clocks (Clock<D>) and resets (Reset<S,P,D?>) directly into its type system. By combining LL(1) backtrack-free syntax, explicit connection arrows, and a unified declaration model, Arch enables static detection of multiple classes of hardware errors at compile time. The language supports direct generation of correct hardware code from natural language prompts and includes a SystemVerilog backend alongside a cycle-accurate C++ simulation toolchain. Evaluated on L1 cache and AXI DMA controller designs in Sky130, Arch outperforms mainstream HDLs in expressiveness, safety, and AI compatibility, with successful synthesis via Yosys and timing validation through OpenSTA.

This work addresses the inefficiency of traditional FPGA design flows, which neglect switching activity data from behavioral simulation and thus struggle to guide power optimization effectively. Existing approaches often rely on fixed thresholds or limited design awareness, incurring significant area overhead. To overcome these limitations, we propose Simopt-Power, a context-aware framework that integrates simulation-derived activity metadata with lightweight structural features—such as timing proximity, logic depth, and fanout—to accurately identify high-impact regions. Rather than using empirical tuning, our method incorporates architecture-aware parameters, including LUT size and mapping constraints, and jointly optimizes area-delay product (ADP) and power-delay product (PDP). Implemented within the open-source Yosys/ABC flow, Simopt-Power achieves an average 6.8% reduction in dynamic power on the Koios deep learning accelerator benchmark while limiting LUT area overhead to within 11.2%.

This work addresses the challenge that RTL code generated in a single pass by large language models (LLMs) often fails to simultaneously achieve functional correctness and power efficiency. To overcome this limitation, the authors propose a novel control framework based on simulated annealing, introducing this optimization mechanism for the first time into LLM-driven hardware design. The approach first filters functionally correct candidate designs through compilation, structural checking, and simulation, and then performs power-performance-area (PPA) co-optimization over this validated subset. By decoupling functional verification from PPA refinement into distinct yet coordinated stages, the method significantly improves both functional correctness rates and the stability and reproducibility of PPA outcomes across eight RTL benchmark designs.

Existing benchmarks struggle to evaluate the end-to-end capabilities of large language models (LLMs) in system-level hardware-software co-design, often assessing hardware and software components in isolation. This work introduces the first benchmark that encompasses the full co-design workflow, requiring an LLM agent to analyze applications, design heterogeneous accelerators, map kernel functions, and deploy a complete system-on-chip (SoC) prototype on an AMD VC707 FPGA. Built upon an open-source SoC platform and a structured repository, the benchmark enables LLMs to jointly reason about and modify both hardware and software stacks. Experimental results show that among five state-of-the-art models, only two successfully generated functional prototypes, achieving a peak speedup of 16.22×, yet with a maximum resource utilization of merely 23.67%, indicating that current LLMs have not yet fully harnessed the potential of hardware acceleration.