dataflow mapping

This work investigates the evolutionary trajectory of algorithmic space complexity across 118 core problems in computer science, encompassing over 800 algorithms. Method: Leveraging a large-scale literature survey, historical complexity data analysis, and theoretical evaluation, the study quantifies trends in memory efficiency improvements relative to hardware advances. Contribution/Results: It is the first to empirically demonstrate that, in 20% of cases, algorithmic space optimization outpaces DRAM latency reduction. The paper introduces the “time–space trade-off Pareto frontier” framework to characterize optimal algorithmic trade-offs over time. Findings confirm that memory efficiency has emerged as a critical constraint in modern algorithm design. To support reproducible research and engineering practice, the authors release an open-source algorithm knowledge base (https://algorithm-wiki.csail.mit.edu), providing standardized benchmarks and decision-support tools for both theoretical analysis and system implementation.

Manual pragma configuration in high-level synthesis (HLS) suffers from low efficiency and an exponentially large search space. Method: This paper proposes the first nonlinear programming (NLP)-based automated pragma insertion framework, jointly optimizing loop-level pragmas—including pipelining, function unit replication, and data caching. It innovatively models discrete pragma configurations as continuous, differentiable variables and constructs analytical performance/resource models with theoretical lower-bound guarantees, solved globally via NLP. Integrated with pragma semantic analysis and the Merlin compiler, and augmented by design-space pruning, the framework explores billion-scale configurations within seconds to minutes. Contribution/Results: Experimental evaluation shows kernel performance approaching hand-tuned implementations, resource estimation error <8%, and latency lower-bound error ≤12%.

AI kernel development faces challenges including complex hardware adaptation and insufficient expressiveness and usability of domain-specific compilers. This paper proposes a composable tiling programming model that—uniquely—decouples dataflow from the scheduling space (thread mapping, memory layout, tensorization, and pipelining). By introducing a unified block-thread abstraction, lightweight scheduling primitive annotations, and dataflow-driven, hardware-aware compilation, our approach jointly optimizes developer productivity and kernel performance. The method bridges the gap between expressive power and engineering practicality in domain-specific compilers. Evaluated on mainstream accelerators—including GPUs and ASICs—our generated AI compute kernels achieve state-of-the-art performance across key workloads, while reducing development cycles significantly. The framework delivers both flexibility in algorithmic expression and high execution efficiency.

To address performance, energy-efficiency, and latency bottlenecks arising from data movement between main memory and processors in data-intensive computing, this paper proposes and systematically advances the practical deployment of Processing-in-Memory (PIM). We introduce a unified PIM architecture framework that innovatively integrates 3D-stacked logic layers, on-die in-memory computing units, memory controller–integrated accelerators, on-chip ECC-enhanced DRAM, and hardware-level RowHammer mitigation. This holistic design significantly reduces data movement overhead, achieving energy-efficiency improvements of several-fold to over an order of magnitude across representative workloads, while ensuring scalability and reliability. The framework establishes a foundation for low-power, high-throughput memory-compute infrastructure applicable to both server and mobile platforms. By bridging architectural innovation with system-level implementation, our work accelerates the transition of PIM from theoretical concept to real-world deployment.

In high-level synthesis (HLS), jointly optimizing code transformations, pragma insertion, and cache-blocking size selection is challenging due to tight coupling, a vast decision space, and difficulty in guaranteeing semantic correctness. Method: This paper proposes the first unified modeling framework that jointly encodes all three aspects as a single, isomorphic optimization problem—supporting “zero-transformation” decisions—and leverages HLS compiler–driven constraint derivation coupled with nonlinear programming (NLP) to automatically and correctly optimize regular loop nests. Contribution/Results: It introduces the first paradigm for co-optimizing transformations, pragmas, and blocking sizes, with built-in semantic equivalence preservation. Evaluated on multiple benchmark kernels, the approach significantly improves quality-of-results (QoR), accurately identifies cases requiring or forbidding transformations, and generates high-performance, formally verifiable optimized code.

To address the low efficiency of compute-intensive image processing algorithms on Software-Configurable Processors (SCPs), this paper proposes an instruction-level hardware-software co-optimization methodology targeting color space conversion and histogram equalization. Leveraging performance profiling to identify computational hotspots, we vectorize and encapsulate critical algorithmic segments into custom extension instructions (EIs), enabling on-chip hardware parallelism on the Stretch SCP platform. Our approach innovatively integrates pixel-level vectorization with automated EI generation, supporting both compiler-driven scheduling and runtime recognition. Experimental results demonstrate over 10× speedup compared to general-purpose processor implementations, achieving high-throughput, real-time image processing. This work establishes a reusable methodology and practical paradigm for algorithm–architecture co-design on SCP platforms.

Deploying deep neural networks on resource-constrained embedded systems presents significant challenges in simultaneously achieving energy efficiency, correctness, and security—particularly in safety-critical domains such as healthcare, where models are vulnerable to fault injection attacks and lack dynamic accuracy guarantees. To address this, this work proposes a hardware-software co-design approach. On the software side, it introduces the first adaptive precision quantization method that jointly ensures real-time operation, dynamic adjustability, and formal correctness, leveraging sensitivity analysis to stabilize decision boundaries. On the hardware side, it designs a customized systolic array supporting left-to-right, most-significant-bit (MSB)-first computation to enhance resilience against bit-flip errors. Experimental results demonstrate the feasibility of the proposed framework, with preliminary findings indicating substantial improvements in both reliability and resource efficiency for edge AI deployments.

This work addresses the lack of dynamic, fine-grained performance throttling mechanisms for AI workloads at the hardware level, where existing software-based defenses are easily bypassed and prior hardware approaches offer only coarse-grained control. The paper proposes a runtime GPU memory subsystem throttling mechanism based on microarchitectural control knobs, enabling architectural-level, fine-grained, and dynamic AI performance suppression for the first time. By orchestrating primitives such as cache way masking, credit-based rate limiting, latency injection, and bank arbitration, the approach jointly regulates L2 cache capacity, latency, bandwidth, and shared memory port access rates. With an overhead of only approximately 10K flip-flops, the mechanism achieves up to 80% performance reduction, stabilizes within 5–80K cycles after throttling initiation, and exerts minimal impact on the rest of the chip.

Hyperdimensional computing (HDC) exhibits inherent resilience to approximation but lacks systematic software-hardware co-designed approximation optimization methodologies. This work proposes ApproxHDC, a framework that introduces compiler-driven automated approximation tuning to HDC for the first time. By extending the existing HPVM-HDC compiler infrastructure, ApproxHDC enables retargetable compilation for diverse hardware platforms, including CPUs, GPUs, and in-memory computing devices such as ReRAM and PCM. The framework integrates efficient search and analytical algorithms to jointly explore the approximation configuration space across software and hardware layers, automatically identifying and deploying high-benefit strategies. Experimental results demonstrate that ApproxHDC significantly enhances performance and energy efficiency of HDC workloads on heterogeneous hardware while incurring minimal accuracy loss, thereby validating its effectiveness and generality.

This work proposes AutoSlim, a novel framework that introduces machine learning–driven graph simplification into symbolic accelerator design to address the high memory overhead and low execution efficiency caused by redundant graph structures. AutoSlim employs a random forest classifier to predict node importance, leveraging automaton graph features and historical execution data to perform data-driven pruning of nondeterministic finite automata. Functional equivalence is rigorously preserved through formal verification. Experimental evaluation on the NAPOLY+ architecture demonstrates that AutoSlim achieves up to 40% reduction in FPGA resource utilization while significantly improving throughput and energy efficiency, all without compromising behavioral correctness.

Deep hierarchical scratchpad memories (SPMs) in LLM accelerators introduce programming complexity and inefficient cache management. Method: This paper proposes a shared system-level cache architecture for many-core AI accelerators, coupled with an application-aware dynamic orchestration mechanism. Innovatively integrating dataflow analysis and cache behavior modeling, it enables predictive replacement, dead-block preemption, bypass decisions, and jitter-resistant scheduling—unified for both shared and private data scenarios. Contribution/Results: Evaluated via cycle-accurate simulation, analytical modeling, and a 15 nm RTL implementation (0.064 mm², 2 GHz), the design preserves programming simplicity while improving cache efficiency over baseline. It achieves up to 1.80× end-to-end speedup, significantly enhancing scalability and many-core collaboration performance.