hardware simulation and verification

To address critical challenges in SoC design—including ambiguous system-level modeling semantics, poor interoperability across heterogeneous computational models (e.g., dataflow and neural networks), and the decoupling of design-space exploration from verification—this paper proposes a co-communication mechanism ensuring semantic consistency across multiple models. The approach establishes an integrated toolchain supporting system-level modeling, simulation-driven verification, hardware-software co-design space exploration, and joint power-performance analysis. Innovatively, it unifies dataflow modeling with system-level abstractions to enable functional correctness verification and quantitative energy-efficiency evaluation for representative applications such as video processing and AI acceleration. Experimental results demonstrate that the methodology significantly improves early-stage SoC design iteration efficiency and enhances the reliability of architectural decision-making.

Reproducing hardware architectures from academic papers remains challenging due to missing source code and the inherent complexity of hardware description languages (HDLs). To address this, we propose a neuro-symbolic graph framework that enables end-to-end generation of synthesizable Verilog RTL and corresponding verification environments directly from unstructured architectural text. Our approach formalizes architectural blueprints as graphs and encodes functional specifications via symbolic rules, jointly generating RTL modules and testbenches while integrating synthesis, timing analysis, and PPA (power-performance-area) evaluation. We introduce ArchSynthBench—the first architecture-to-hardware synthesis benchmark—comprising 50 system-level circuits and 600 modules, and decouple design and verification to enhance correctness and debuggability. Experiments show that all generated RTL meets timing constraints, matches original performance metrics, and achieves higher code completion and architectural understanding accuracy than state-of-the-art baselines (e.g., VerilogCoder).

To address the bottleneck in VLSI design where RTL-stage PPA (power, performance, area) estimation relies on time-consuming full synthesis—hindering rapid iteration—this paper proposes the first pre-synthesis machine learning framework operating directly on HDL source code. Our method introduces a bit-level Simple Operation Graph (SOG) representation that explicitly models the semantic mapping between RTL constructs and post-synthesis structures. We further design a standard-cell-library-aware tree-based architecture enabling end-to-end PPA prediction solely from Verilog code and library files, without requiring toggle information or synthesis intermediates. Evaluated on 147 industrial-scale RTL designs, our framework achieves 98% accuracy for worst negative slack (WNS), 98% for total negative slack (TNS), and 90% for power estimation—significantly outperforming prior approaches. The method demonstrates strong generalization across diverse designs and high engineering practicality.

This work addresses the challenge that large language models (LLMs) often generate erroneous RTL code due to ambiguous or misinterpreted specifications, with such errors typically surfacing only during simulation and proving difficult to trace. To mitigate this, the paper proposes VeriRefine, a novel approach that first refines informal specifications into explicit Abstract Signal Transition Functions (ASTFs)—serving as a verifiable prelude to RTL generation. The method incorporates a five-layer auditing mechanism to validate design intent across dimensions including completeness, consistency, and FSM integrity, and enables targeted debugging by tracing simulation failures back to either specification misunderstandings or coding errors. Evaluated on RTLLM v2.0 and VerilogEval-Human v2, VeriRefine achieves functional correctness rates of 94.0% and 98.1%, respectively, substantially enhancing the reliability and synthesizability of LLM-generated RTL.

This work addresses the challenge that large language models (LLMs) often introduce semantic or logical errors when generating hardware RTL code, failing to meet the stringent reliability requirements of chip design. To overcome this limitation, the paper proposes a novel hardware generation framework that integrates LLMs with formal methods, uniquely combining LLM-driven iterative refinement with formal verification. The approach leverages predefined transformation rules to guide the LLM in progressively refining high-level specifications into RTL code that is formally verifiable for correctness. This integration enhances both the interpretability and reliability of the code generation process. Experimental results demonstrate that the method is not only effective but also efficient in producing correct RTL implementations, thereby offering a promising pathway toward trustworthy LLM-assisted hardware design.

This work addresses the inefficiencies and semantic inconsistencies arising from separately implementing driver and monitor programs in traditional hardware module testing. To overcome this, the authors propose a domain-specific language (DSL) tailored to hardware communication protocols, which enables the unified specification of both driver and monitor logic through an imperative syntax, thereby ensuring their semantic consistency for the first time. Building upon this DSL, they develop a prototype tool that leverages waveform parsing and transaction-level trace inference techniques to accurately reconstruct protocol-compliant transaction sequences from raw signal waveforms. Experimental results demonstrate that the approach significantly improves development efficiency, with further validation planned on real-world interconnect protocols such as Wishbone and AXI-Stream.

This work proposes a novel approach to hardware security verification by automatically constructing end-to-end information flow paths from register transfer level (RTL) trace data. Unlike conventional information flow analyses that merely detect whether data flows between registers, the proposed method reconstructs complete propagation pathways of sensitive information at the RTL trace level for the first time. By integrating information flow tracking with specification mining techniques, the framework automatically generates and verifies security properties. This paradigm overcomes the limitations of pairwise flow detection, substantially enhancing the automation, precision in violation detection, and efficiency of system-wide security evaluation in hardware designs.

This work addresses the challenge that existing LLM-driven hardware generation methods struggle to support the semantic evolution of trusted legacy RTL designs. The authors propose an executable-contract-centered framework for hardware evolution, which translates new functional requirements into formally scrutinized contracts and realizes controlled, verifiable iterations from behavioral specifications to RTL modifications through a four-phase Specify-Plan-Implement-Validate workflow. Key technical innovations include executable-contract-guided evolution, mutation-based semantic probing, cross-version semantic differential analysis, and proof-driven RTL repair and verification. Evaluated on a TPU datapath module undergoing data format evolution, the approach successfully achieves functional convergence from legacy RTL to the updated version while ensuring correctness through contract-driven verification.