custom silicon

To address critical challenges in SoC design—including ambiguous system-level modeling semantics, poor interoperability across heterogeneous computational models (e.g., dataflow and neural networks), and the decoupling of design-space exploration from verification—this paper proposes a co-communication mechanism ensuring semantic consistency across multiple models. The approach establishes an integrated toolchain supporting system-level modeling, simulation-driven verification, hardware-software co-design space exploration, and joint power-performance analysis. Innovatively, it unifies dataflow modeling with system-level abstractions to enable functional correctness verification and quantitative energy-efficiency evaluation for representative applications such as video processing and AI acceleration. Experimental results demonstrate that the methodology significantly improves early-stage SoC design iteration efficiency and enhances the reliability of architectural decision-making.

ASIC development faces challenges in IP reuse and lacks integrated hardware-software co-verification and unified build infrastructure. Method: This paper introduces SoCMake—the first unified SoC build system supporting cross-compilation of Chisel/SystemRDL hardware descriptions with C/C++/assembly code. It integrates RTL generation, simulation, firmware compilation, and SoC configuration into a single workflow, overcoming the limited software compilation support of conventional hardware build tools. By deeply embedding SystemC, the RISC-V toolchain, and CMake’s extensibility framework, SoCMake enables automated, abstraction-level–aware co-building across hardware description → RTL → firmware. Contribution/Results: SoCMake has successfully accelerated iterative deployment of radiation-tolerant RISC-V SoCs in high-energy physics applications. After open-sourcing, it has become a de facto standard for generic SoC generation, reducing overall SoC development time by over 40% in empirical evaluations.

Software developers face significant challenges integrating custom hardware—such as AI accelerators—into applications, primarily due to high hardware design expertise requirements and a fundamental abstraction mismatch between software and hardware layers. Method: This paper introduces an end-to-end chip auto-generation methodology tailored for software developers. It accepts high-level object-oriented specifications as input and establishes a one-to-one mapping between software objects and physical chip regions to ensure abstraction consistency. We propose the novel “software–chip structural alignment” paradigm, coupled with object-aligned floorplanning, vertically integrated IP modular construction, and formal verification of hardware interactions via a sequence-based type system. Contribution/Results: The approach enables novice developers to produce synthesizable chip designs while guaranteeing semantic consistency between software behavior and hardware implementation, as well as correctness of hardware communication. It substantially lowers the domain-specific knowledge barrier for hardware design without compromising functional fidelity or correctness guarantees.

Hardware description language (HDL) understanding—particularly for VHDL in high-performance microprocessor design—lacks effective AI support. Method: This paper proposes a large language model (LLM) customization framework specifically for HDLs. Its core innovations include: (1) a novel VHDL-specific Extended Pre-Training (EPT) paradigm to enhance modeling of hardware semantics such as sequential logic and parallel constructs; (2) an LLM-as-a-judge automated evaluation framework achieving high agreement with human experts (Spearman’s ρ = 0.92); and (3) a domain-adapted benchmark suite and expert-aligned evaluation protocol. Results: Experiments show EPT improves expert-assessed accuracy from a baseline of 43% to 69%; instruction fine-tuning further raises it to 71%, with projections exceeding 85% on a newly initialized base model—significantly bridging the technical gap in intelligent VHDL comprehension.

To address low efficiency, insufficient coverage, and poor RTL bug detection in FSM-based chip functional verification, this paper proposes an EDA-feedback-driven, closed-loop LLM testbench generation method. Initial testbenches are generated using GPT-3.5 or GPT-4; then, real-time signal-level feedback—including code and state coverage metrics and error diagnostics—from commercial EDA tools (e.g., Synopsys VCS) is integrated into the prompt engineering process, enabling iterative refinement. This work pioneers deep integration of EDA tool feedback into the LLM generation pipeline, supporting coverage-guided automated test generation and concurrent RTL-level bug detection. Evaluated on multiple industrial-grade FSM designs, the method improves code and state coverage by 20–35% over baseline approaches and successfully identifies timing and control-logic bugs missed by manual verification. The approach significantly enhances both verification efficiency and reliability.

This work addresses the longstanding limitations in chip design education imposed by proprietary EDA tools, PDKs, and IP blocks, which hinder the development of domain-specific SoC engineers with full-stack practical skills. To overcome this barrier, the authors present the first end-to-end open-source SoC tapeout flow for educational use, built around the highly customizable RISC-V platform Croc. The framework integrates open-source SystemVerilog IP, a 130nm open PDK, and a complete open-source EDA toolchain, enabling multi-dimensional customization—including instruction set extensions, coprocessors, and peripherals. In its inaugural deployment, 65 students completed 33 projects, yielding 30 manufacturable layouts and 5 successful tapeouts. The baseline chip has undergone silicon validation, demonstrating functionality and performance comparable to proprietary solutions, thereby significantly lowering the barrier to SoC design and validating the feasibility of a fully open-source design methodology.