asic

To address the low efficiency of manual exploration and the difficulty of balancing performance gains against hardware overhead in RISC-V custom instruction design, this paper proposes CIDRE—a fully automated toolchain for end-to-end custom instruction synthesis, from dynamic hotspot analysis and pattern extraction to automatic generation of synthesizable nML hardware descriptions. Methodologically, CIDRE integrates a microarchitecture-aware instruction identification mechanism with an ASIP co-design flow, enabling joint evaluation of performance, area, and power. Evaluated on Embench and MiBench benchmarks, it achieves an average speedup of 1.83× (up to 2.47×) with custom instruction area overhead ≤24%, significantly outperforming existing manual or semi-automated approaches. Key contributions include: (1) the first end-to-end, microarchitecture-aware framework for automated custom instruction generation; (2) support for evaluatable and synthesizable nML output; and (3) empirical validation of the approach’s practicality and scalability under energy-efficiency and area constraints.

This study addresses the inherent challenge in hardware design of balancing complexity management with model accuracy. To this end, it proposes an abstraction-centric methodology that associates discretization techniques with pre-clustered elements, such as transistors. By integrating lumped modeling, value discretization, and time discretization, the approach establishes a well-defined hierarchy of abstractions. The primary contribution of this work is a standardized design methodology that enhances productivity by simplifying model complexity and improving simulation efficiency while defining effective constraints. Consequently, this framework significantly strengthens the capacity to manage complex systems in digital design, thereby advancing overall engineering productivity.

To address critical challenges in SoC design—including ambiguous system-level modeling semantics, poor interoperability across heterogeneous computational models (e.g., dataflow and neural networks), and the decoupling of design-space exploration from verification—this paper proposes a co-communication mechanism ensuring semantic consistency across multiple models. The approach establishes an integrated toolchain supporting system-level modeling, simulation-driven verification, hardware-software co-design space exploration, and joint power-performance analysis. Innovatively, it unifies dataflow modeling with system-level abstractions to enable functional correctness verification and quantitative energy-efficiency evaluation for representative applications such as video processing and AI acceleration. Experimental results demonstrate that the methodology significantly improves early-stage SoC design iteration efficiency and enhances the reliability of architectural decision-making.

Large language models (LLMs) lack critical capabilities—such as code execution, debugging, and long-term memory—for practical application in ASIC design. To address this, we propose the first autonomous multi-agent system tailored for digital hardware design. Our method integrates specialized sub-agents for RTL generation, simulation-based verification, OpenLane-based physical implementation, and Caravel chip packaging, operating within a secure hardware design sandbox. We further introduce a vector database supporting long-term memory and community knowledge retrieval. Additionally, we release ASIC-Agent-Bench—the first benchmark for hardware design agents. Experiments demonstrate that a Claude 3 Sonnet–based instantiation of our system successfully completes diverse, end-to-end ASIC tasks—including synthesis, place-and-route, and tapeout preparation—within the closed sandbox. Results show substantial improvements in design efficiency and validate the feasibility and practicality of multi-agent architectures in the open-source silicon ecosystem.

ASIC development faces challenges in IP reuse and lacks integrated hardware-software co-verification and unified build infrastructure. Method: This paper introduces SoCMake—the first unified SoC build system supporting cross-compilation of Chisel/SystemRDL hardware descriptions with C/C++/assembly code. It integrates RTL generation, simulation, firmware compilation, and SoC configuration into a single workflow, overcoming the limited software compilation support of conventional hardware build tools. By deeply embedding SystemC, the RISC-V toolchain, and CMake’s extensibility framework, SoCMake enables automated, abstraction-level–aware co-building across hardware description → RTL → firmware. Contribution/Results: SoCMake has successfully accelerated iterative deployment of radiation-tolerant RISC-V SoCs in high-energy physics applications. After open-sourcing, it has become a de facto standard for generic SoC generation, reducing overall SoC development time by over 40% in empirical evaluations.

本文提出了一种基于大型语言模型的行为驱动硬件开发流程，通过定义形式验证Gherkin场景来减少自然语言规范的模糊性，提高硬件设计的形式验证效果。

本文探讨了学术界与产业界如何通过重视基础硅设计原理来适应AI原生时代的挑战和机遇，促进社区转型。

This study addresses the challenges of semantic alignment and tool integration in automating hardware verification, particularly concerning assertion generation, debugging, and formal reasoning. To overcome these limitations, this work proposes a neuro-symbolic hybrid architecture that leverages large language models (LLMs) as core orchestration components. By integrating prompt engineering, retrieval-augmented generation, agentic workflows, and SAT/SMT solver optimization techniques, the proposed framework establishes semantic consistency as a critical breakthrough for automated verification pipelines. Furthermore, this paper systematically reviews the application paradigms of LLMs across the entire hardware verification workflow and empirically validates the effectiveness of the hybrid architecture. Finally, it provides an in-depth analysis of the limitations inherent in current evaluation methodologies and outlines promising directions for future research in AI-driven electronic design automation.

This study addresses the lack of industrial-grade EDA support and limited high-level synthesis for asynchronous circuits by implementing automated synthesis from imperative programs to asynchronous hardware based on the AHIR framework. The proposed methodology employs a delay-insensitive controller coupled with a single-rail datapath architecture. Furthermore, it introduces 1-safe Petri net modeling and formally proves the necessary and sufficient conditions for timing constraints, while maintaining full compatibility with standard ASIC toolchains. As an end-to-end demonstration, the AES encryption algorithm is synthesized, and post-layout simulations validate both the functional correctness and performance metrics of the resulting circuit. This work ultimately provides a comprehensive solution for the automated design of asynchronous circuits.

This study investigates whether low-level optimizations in high-level hardware description language (HDL) designs justify their impact on ASIC area and additional implementation effort. Using the functional HDL Clash, we design bit-serial multiply-accumulate (MAC) units across sixteen configurations and conduct synthesis experiments to quantitatively compare circuit sizes between high-level abstractions and low-level Verilog strategies. Results demonstrate that the area overhead of certain high-level constructs is negligible, validating the feasibility of employing full-featured programming languages for hardware design. Nevertheless, an inherent area penalty persists relative to hand-optimized Verilog crafted by experienced engineers. This work provides quantitative evidence for evaluating the trade-offs between abstraction levels and low-level optimizations in modern HDL-based design flows.