constraint-driven layout generation

At advanced technology nodes, the tight coupling between layout and electrical performance in analog circuits poses significant challenges for automated placement. This work proposes a row-height-quantized cell-based layout synthesis methodology, systematically introducing row-height quantization into analog circuit design for the first time. By optimizing row-height structures, modeling layout constraints, and enabling automatic mapping of analog modules onto quantized rows, the approach effectively bridges the performance gap between schematic and post-layout stages. Experimental results across multiple test cases demonstrate that the method achieves performance close to manual custom design, reducing the schematic-to-post-layout performance deviation by up to 68.5% and decreasing area overhead by as much as 24.1%.

This work addresses the challenges in automated PCB schematic design, which are hindered by heterogeneous signal processing, difficulties in modeling realistic IC package constraints, and a lack of open-source datasets and validation methodologies. The authors propose the first training-free framework for automatic schematic generation, integrating large language model agents with constraint-guided synthesis. By leveraging domain-specific prompts, the system iteratively generates circuit code and constructs a knowledge graph derived from IC datasheets to enable precise validation of both topological structure and pin semantics. The approach supports mixed-signal designs encompassing digital, analog, and power circuits, demonstrating significant improvements in design accuracy and computational efficiency across 23 real-world tasks, thereby establishing a novel training-free paradigm for PCB schematic generation.

This paper addresses the automated layout design problem for stripboard (perfboard) circuits. We propose a declarative synthesis and multi-objective optimization approach based on Answer Set Programming (ASP). The problem is modeled holistically to enforce electrical connectivity, geometric constraints, and minimization of wire crossings. A two-stage solving strategy is adopted: first ensuring layout feasibility, then jointly optimizing board area and the number of component jumper connections (i.e., through-hole interconnections). Unlike traditional heuristic methods, our declarative formulation naturally encodes complex domain constraints, yielding higher-quality and more manufacturable solutions. Experimental evaluation across circuits of varying complexity demonstrates that our method consistently produces compact, low-crossing, and solder-friendly layouts—achieving an average 18.7% reduction in board area and a 32.4% decrease in jumper count. The approach is particularly suitable for electronic prototyping and educational applications.

This work addresses the challenge that existing large language models struggle to simultaneously satisfy stringent geometric, routing, and electrical connectivity constraints in dense PCB layout design. To bridge this gap, we introduce OmniLayout, the first multimodal benchmark specifically tailored for PCB layout, which jointly models schematic diagrams and physical layouts. The benchmark encompasses four constraint-aware reasoning tasks designed to systematically evaluate model capabilities in geometric reasoning, routability, preservation of electrical functionality, and tool invocation. Integrating industrial-scale layout data, geometric constraint modeling, routing analysis, and circuit verification, our framework exposes critical limitations of current models—particularly their weak geometric reasoning, poor routing optimization, and insufficient functional consistency—thereby filling a crucial void in evaluating multimodal collaborative reasoning within electronic design automation.

Analog circuit topology synthesis faces two key challenges: existing methods rely on imprecise specifications, neglect engineering constraints, and oversimplify design as graph or code generation—divorcing it from real expert decision-making. This paper introduces the first practical, LLM-driven topology synthesis framework: it embeds domain expertise into large language models, leverages a measured SPICE subcircuit library as primitives, and performs end-to-end topology generation via stepwise block selection, interconnection, chain-of-thought guidance, and iterative SPICE-level validation and correction. Key contributions include: (1) the first formalization of authentic analog design workflow as an LLM agent behavior; (2) construction of the first high-quality benchmark comprising 30 measured circuit cases; and (3) introduction of SPICE-native representation and subcircuit-constrained search. Our method achieves 40% success rate on synthetic data and 23% on real-world data—substantially outperforming GPT-4o (3% and 3%, respectively).

This work addresses the longstanding challenges in traditional analog circuit design, which heavily relies on manual effort across disconnected stages—topology selection, sizing, and layout—hindering holistic optimization. To overcome this, the authors propose PANDA, a novel framework that integrates large language models (LLMs) into end-to-end analog design automation, enabling direct translation of high-level design intent into final layout. PANDA uniquely captures cross-stage dependencies through guided topology synthesis, substructure-aware sizing, and constraint-driven layout generation, thereby shifting the design paradigm from algorithm-centric to intent-centric. Experimental results demonstrate that PANDA reduces design cycles from days or weeks to mere hours while significantly improving circuit performance.

This work addresses the ongoing challenge of automatically translating natural language specifications into editable printed circuit board (PCB) schematics for embedded and IoT development. It presents the first end-to-end approach that leverages tool-augmented large language model reasoning, integrating component library retrieval, datasheet knowledge extraction, execution validation, and structural-semantic verification to generate KiCad-compliant schematics. The system supports iterative refinement through an interactive web interface and achieves a pass@1 rate of 0.90 and a pass@5 rate of 1.00 across 20 embedded schematic generation tasks. This method efficiently produces high-quality initial drafts suitable for early-stage prototype review, substantially advancing the state of hardware design automation.

Current large language models exhibit significant limitations in handling complex PCB routing tasks that must satisfy geometric, topological, and electrical constraints, and there is a lack of evaluation benchmarks grounded in real-world industrial scenarios. To address this gap, this work proposes OmniRouting—the first large-scale reasoning benchmark for PCB routing—comprising 1,681 industrial schematic–layout paired designs that integrate semantic and multimodal information along with joint schematic–layout constraints. The benchmark defines four progressively challenging constraint-aware tasks: geometric routing, design rule compliance, electrical functionality preservation, and tool-augmented agent reasoning, incorporating PCB geometry, component placement, netlists, stackup configurations, and EDA tool interfaces. Experiments reveal substantial deficiencies in existing models regarding path planning, rule adherence, and electrical connectivity. All data, evaluation code, and tool interfaces are publicly released to advance AI-driven PCB design research.

This work addresses the longstanding challenge in PCB schematic design, which heavily relies on manual effort and lacks effective methods for automatically generating editable circuit diagrams from natural language. We propose SchGen, the first large language model tailored for this task, introducing a novel semantic-anchored code representation that reframes the geometry-driven generation problem as a semantic matching task. To support training, we construct a large-scale paired dataset linking natural language descriptions to schematics. SchGen integrates pin-name-aware routing with relative component layout to enable end-to-end generation of editable schematics from text. Experimental results demonstrate that SchGen significantly outperforms existing representation schemes and even larger general-purpose language models in terms of wiring accuracy and functional correctness, highlighting the critical role of domain-specific semantic representations in complex hardware generation tasks.

This work addresses the inefficiency and heavy reliance on expert knowledge in analog circuit design, particularly within the nonlinear, high-dimensional search space where existing large language model (LLM) approaches struggle to jointly handle topology generation and sizing optimization. To overcome these limitations, the authors propose AaLLM, an end-to-end multi-agent framework featuring a Designer–Critic–Evaluator triad that integrates retrieval-augmented generation (RAG) with automated knowledge base construction to directly translate user specifications into complete netlists. The approach significantly enhances both innovation and efficiency: generated circuits achieve figures of merit (FoMs) comparable to or exceeding those of human-designed counterparts—by up to threefold—while reducing SPICE simulation calls by 3–4.5× and accelerating overall runtime by 40×.