floorplanning and placement

Existing learning-based approaches for analog IC floorplanning suffer from strong coupling between floorplanning and routing, and lack explicit routing awareness. Method: This paper proposes an automated floorplanning engine integrating reinforcement learning (RL) with relational graph convolutional networks (R-GCN). It introduces high-resolution grid partitioning, precise pin modeling, and a dynamic routing-resource estimation algorithm to explicitly model congestion evolution during training. Contribution/Results: To the best of our knowledge, this is the first learning-based framework achieving joint optimization of routability and area efficiency. Experiments demonstrate that, compared to state-of-the-art learning methods, the proposed approach reduces dead space by 13.8%, total wirelength by 40.6%, and improves routing success rate by 73.4%, meeting industrial usability requirements.

This work addresses the challenge of minimizing wirelength while resolving module overlaps in VLSI floorplanning by proposing a three-stage fixed-outline placement framework that synergistically integrates non-convex and convex optimization techniques. The approach begins with a quadratic placement to generate a topology-aware initial solution, followed by a joint optimization of wirelength and overlap using an Adam-based projected gradient method. Finally, legalization is efficiently achieved through a logarithmic barrier convex model derived from horizontal and vertical constraint graphs. This framework represents the first unified placement flow that cohesively combines non-convex and convex optimization within a single pipeline, significantly enhancing wirelength quality. Experimental results on MCNC, GSRC, and HB+ benchmarks demonstrate state-of-the-art performance, with average HPWL improvements of at least 1% and 5% over existing methods.

Existing chip floorplanning methods are decoupled from subsequent physical design stages, leading to suboptimal intra-module placement and excessive inter-module feedthroughs. This work proposes a PPA-aware, three-stage orthogonal floorplanning methodology that jointly optimizes intra-module component placement and inter-module through-signal routing for the first time during floorplanning, incorporating variable-shape local refinement and cross-stage feedback. Key techniques include wiremask and position masking, zero-white-space placement, and a fast-tree-search-based co-placement algorithm for macros and standard cells. Experimental results demonstrate a 6% reduction in half-perimeter wirelength (HPWL), 5.16% and 29.15% reductions in feedthrough pins (FTpin) and feedthrough modules (FTmod), respectively, and a 14% improvement in placement quality—significantly enhancing layout awareness and enabling tighter co-optimization of wirelength and feedthroughs.

This study investigates the structural conditions under which outerplanar graphs admit area-universal rectangular layouts—layouts that, for any prescribed assignment of rectangle areas, admit a combinatorially equivalent realization. By integrating techniques from graph theory, computational geometry, and combinatorial optimization, the work establishes necessary and sufficient structural conditions for an outerplanar graph to be area-universal and presents a constructive algorithm to generate such layouts. This paper provides the first complete characterization of area-universality for outerplanar graphs, thereby filling a fundamental gap in the theory of area-universal layout representations. The proposed algorithm efficiently constructs layouts that realize arbitrary area assignments while preserving the prescribed combinatorial structure.

This work addresses the challenge that existing large language models struggle to simultaneously satisfy stringent geometric, routing, and electrical connectivity constraints in dense PCB layout design. To bridge this gap, we introduce OmniLayout, the first multimodal benchmark specifically tailored for PCB layout, which jointly models schematic diagrams and physical layouts. The benchmark encompasses four constraint-aware reasoning tasks designed to systematically evaluate model capabilities in geometric reasoning, routability, preservation of electrical functionality, and tool invocation. Integrating industrial-scale layout data, geometric constraint modeling, routing analysis, and circuit verification, our framework exposes critical limitations of current models—particularly their weak geometric reasoning, poor routing optimization, and insufficient functional consistency—thereby filling a crucial void in evaluating multimodal collaborative reasoning within electronic design automation.

针对VLSI物理设计中的自动宏放置挑战，提出PlaceReasoner-Beta框架，通过视觉-语言模型、几何验证器和物理验证器等组件实现闭环推理优化。

Early exploration of 3D integrated circuit architectures has been hindered by inaccurate modeling of layout-induced thermal, interconnect, and cache effects, leading to unreliable predictions of actual operating frequency and performance. This work proposes CLIP-3D, a left-shifted design flow that maps architectural configurations to physically aware representations without requiring signoff tools, and jointly optimizes cross-layer macro allocation and floorplanning through a thermal-aware placer. Its key innovation lies in introducing, for the first time, a closed-loop, analytical continuous-frequency model that directly targets actual BIPS (billion instructions per second) in joint optimization, eliminating reliance on manually weighted proxy objectives. By integrating McPAT, CACTI, and a HotSpot-compatible 3D thermal model, CLIP-3D substantially improves performance estimation accuracy and enables efficient architectural-level screening of designs free from thermal or interconnect-induced frequency throttling.

This study addresses the inadequacy of post-layout mapping decisions in accounting for surrounding timing constraints, fanout loads, and interconnect effects. To overcome this limitation, it proposes a local remapping framework that couples discrete search with physical feedback. The approach first isolates timing-critical regions and employs continuous relaxation to prune the search space. It then leverages mixed-integer programming to jointly optimize logic cuts, signal polarities, and library cell selection, modeling delays based on estimated placements. Finally, a closed-loop verification process encompassing legalization, routing parasitic estimation, and timing analysis is conducted to guide subsequent iterative searches. This work thereby achieves precise, physically aware, and timing-driven logic remapping.

This work proposes OrderPlace, a novel framework that treats macro placement order as a learnable optimization dimension, overcoming the limitations of traditional static heuristics which often lead to irreversible suboptimal constraints due to early placement decisions. By integrating large language model–guided evolutionary algorithms, code-level policy generation, and a lightweight surrogate evaluator, OrderPlace efficiently explores dynamic and diverse placement sequencing strategies. Evaluated on the ISPD 2005 benchmark suite, the method reduces wirelength by 34.04% and 14.08% compared to WireMask-EA and EGPlace, respectively, demonstrating the superior effectiveness of the discovered placement policies.

Current large language models exhibit significant limitations in handling complex PCB routing tasks that must satisfy geometric, topological, and electrical constraints, and there is a lack of evaluation benchmarks grounded in real-world industrial scenarios. To address this gap, this work proposes OmniRouting—the first large-scale reasoning benchmark for PCB routing—comprising 1,681 industrial schematic–layout paired designs that integrate semantic and multimodal information along with joint schematic–layout constraints. The benchmark defines four progressively challenging constraint-aware tasks: geometric routing, design rule compliance, electrical functionality preservation, and tool-augmented agent reasoning, incorporating PCB geometry, component placement, netlists, stackup configurations, and EDA tool interfaces. Experiments reveal substantial deficiencies in existing models regarding path planning, rule adherence, and electrical connectivity. All data, evaluation code, and tool interfaces are publicly released to advance AI-driven PCB design research.