synthesis and place-and-route

Congestion in VLSI placement is typically identifiable only after detailed routing, rendering conventional validation workflows time-consuming and costly. This work proposes VeriHGN, a novel framework that for the first time deeply integrates the logical connectivity of circuit netlists with physical placement grids into a unified, enhanced heterogeneous graph representation, overcoming the limitations of prior loosely coupled modeling approaches. Leveraging a heterogeneous graph neural network, the method achieves state-of-the-art performance on industrial benchmarks—including ISPD2015, CircuitNet-N14, and CircuitNet-N28—demonstrating superior accuracy and correlation in early-stage congestion prediction compared to existing techniques.

Reproducing hardware architectures from academic papers remains challenging due to missing source code and the inherent complexity of hardware description languages (HDLs). To address this, we propose a neuro-symbolic graph framework that enables end-to-end generation of synthesizable Verilog RTL and corresponding verification environments directly from unstructured architectural text. Our approach formalizes architectural blueprints as graphs and encodes functional specifications via symbolic rules, jointly generating RTL modules and testbenches while integrating synthesis, timing analysis, and PPA (power-performance-area) evaluation. We introduce ArchSynthBench—the first architecture-to-hardware synthesis benchmark—comprising 50 system-level circuits and 600 modules, and decouple design and verification to enhance correctness and debuggability. Experiments show that all generated RTL meets timing constraints, matches original performance metrics, and achieves higher code completion and architectural understanding accuracy than state-of-the-art baselines (e.g., VerilogCoder).

This work addresses the challenge that large language models (LLMs) often introduce semantic or logical errors when generating hardware RTL code, failing to meet the stringent reliability requirements of chip design. To overcome this limitation, the paper proposes a novel hardware generation framework that integrates LLMs with formal methods, uniquely combining LLM-driven iterative refinement with formal verification. The approach leverages predefined transformation rules to guide the LLM in progressively refining high-level specifications into RTL code that is formally verifiable for correctness. This integration enhances both the interpretability and reliability of the code generation process. Experimental results demonstrate that the method is not only effective but also efficient in producing correct RTL implementations, thereby offering a promising pathway toward trustworthy LLM-assisted hardware design.

Software developers face significant challenges integrating custom hardware—such as AI accelerators—into applications, primarily due to high hardware design expertise requirements and a fundamental abstraction mismatch between software and hardware layers. Method: This paper introduces an end-to-end chip auto-generation methodology tailored for software developers. It accepts high-level object-oriented specifications as input and establishes a one-to-one mapping between software objects and physical chip regions to ensure abstraction consistency. We propose the novel “software–chip structural alignment” paradigm, coupled with object-aligned floorplanning, vertically integrated IP modular construction, and formal verification of hardware interactions via a sequence-based type system. Contribution/Results: The approach enables novice developers to produce synthesizable chip designs while guaranteeing semantic consistency between software behavior and hardware implementation, as well as correctness of hardware communication. It substantially lowers the domain-specific knowledge barrier for hardware design without compromising functional fidelity or correctness guarantees.

To address critical challenges in SoC design—including ambiguous system-level modeling semantics, poor interoperability across heterogeneous computational models (e.g., dataflow and neural networks), and the decoupling of design-space exploration from verification—this paper proposes a co-communication mechanism ensuring semantic consistency across multiple models. The approach establishes an integrated toolchain supporting system-level modeling, simulation-driven verification, hardware-software co-design space exploration, and joint power-performance analysis. Innovatively, it unifies dataflow modeling with system-level abstractions to enable functional correctness verification and quantitative energy-efficiency evaluation for representative applications such as video processing and AI acceleration. Experimental results demonstrate that the methodology significantly improves early-stage SoC design iteration efficiency and enhances the reliability of architectural decision-making.

This work proposes a novel approach to hardware security verification by automatically constructing end-to-end information flow paths from register transfer level (RTL) trace data. Unlike conventional information flow analyses that merely detect whether data flows between registers, the proposed method reconstructs complete propagation pathways of sensitive information at the RTL trace level for the first time. By integrating information flow tracking with specification mining techniques, the framework automatically generates and verifies security properties. This paradigm overcomes the limitations of pairwise flow detection, substantially enhancing the automation, precision in violation detection, and efficiency of system-wide security evaluation in hardware designs.

This work addresses the inefficiencies and semantic inconsistencies arising from separately implementing driver and monitor programs in traditional hardware module testing. To overcome this, the authors propose a domain-specific language (DSL) tailored to hardware communication protocols, which enables the unified specification of both driver and monitor logic through an imperative syntax, thereby ensuring their semantic consistency for the first time. Building upon this DSL, they develop a prototype tool that leverages waveform parsing and transaction-level trace inference techniques to accurately reconstruct protocol-compliant transaction sequences from raw signal waveforms. Experimental results demonstrate that the approach significantly improves development efficiency, with further validation planned on real-world interconnect protocols such as Wishbone and AXI-Stream.

This work proposes the first end-to-end automated framework that translates natural language specifications directly into GDSII layouts, addressing the slow pace of hardware prototyping caused by the gap between high-level specifications and register-transfer level (RTL) implementations. The framework leverages a multi-engine large language model to generate and verify synthesizable HDL code, which is then automatically synthesized, placed, and routed through the open-source OpenLane physical design flow. Evaluated on the ISCAS’85/89 benchmark suites, the approach achieves up to 36% reduction in area, 35% lower delay, and 70% power savings compared to baseline designs. By significantly lowering the barrier to ASIC design, this framework advances the democratization of hardware development.