area and power estimation

This study challenges the conventional assumption that device power consumption is predominantly determined by hardware, instead investigating the influence of user behavior on system-level energy usage. Leveraging Intel telemetry data, the research employs exploratory data analysis and linear regression models to compare power consumption patterns across users in different countries, with a focus on the United States and China. The findings reveal a statistically significant association between user behavior and overall power draw, demonstrating that behavioral factors exert a non-negligible impact on energy consumption. This insight offers a novel perspective for green computing initiatives and provides empirical evidence to inform stakeholders such as Intel in refining energy-efficiency strategies and mitigating environmental impact.

To address the challenges of low accuracy, high overhead, and slow response in online power estimation under enhanced hardware heterogeneity and increased parallelism for embedded systems, this paper proposes a lightweight system-level power modeling and real-time monitoring method based on Performance Monitoring Counters (PMCs). The method constructs a modular, linear-correlation-driven power model that requires no microarchitectural details and supports flexible, rapid reconfiguration across DVFS states. Integrated with the Linux kernel-level framework Runmeter, it enables low-overhead PMC sampling and runtime power estimation. Experimental results demonstrate an average power estimation error of only 7.5%, energy error of 1.3%, and worst-case kernel monitoring overhead below 0.7%. This enables effective closed-loop task scheduling and workload-aware DVFS control.

This work addresses the challenge of achieving efficient and fine-grained module-level power estimation for CPUs during early design stages, where traditional approaches rely on simulation or post-silicon analysis and thus lack agility. The paper introduces, for the first time, the use of large language models for CPU power modeling, proposing a hierarchical source-code-level surrogate model that directly extracts architectural hierarchy, module interconnections, configuration parameters, and workload context from RTL code. This enables accurate per-module power prediction without requiring simulation during inference. Experimental evaluation on the open-source XiangShan processor family demonstrates that the proposed method delivers highly accurate and efficient module-level power estimates across diverse configurations and workloads, significantly outperforming conventional workflows by substantially accelerating early-stage design evaluation while maintaining high fidelity.

Processor thermal design power (TDP) is widely misused as a proxy for actual power consumption in physics simulations, leading to inaccurate energy-efficiency assessments. Method: This study conducts the first empirical power and energy measurements of major production-scale physics simulation codes on heterogeneous exascale supercomputers at LLNL and Sandia. Leveraging multi-granularity energy modeling, cross-platform benchmarking, and real-time monitoring across commercial and advanced CPU–GPU heterogeneous nodes, it systematically quantifies runtime energy efficiency. Contribution/Results: Under typical simulation workloads, measured power draw is only 30–60% of TDP—substantially lower than nominal ratings. This work challenges the longstanding practice of substituting TDP for measured power, establishing an empirically grounded methodology for evaluating energy efficiency in exascale systems. It provides critical, reproducible, and generalizable energy benchmarks to guide hardware deployment and energy-aware optimization, thereby advancing low-carbon scientific computing.

This study addresses the invisibility of energy consumption in software build pipelines and the limitations of existing estimation-based tools that cannot decompose energy usage across individual build phases. To overcome these challenges, this work proposes an open-source command-line tool enabling hardware-level energy measurement with user-defined phase attribution. By monitoring standard output for fine-grained phase-level energy analysis, the approach transcends measurement constraints inherent to cloud environments. Technically, it integrates Intel RAPL, NVML, and Maven plugins with pattern matching to achieve precise energy tracking. Validation on the Gson project successfully generated comprehensive phase-resolved energy profiles for both cold and warm builds. Ultimately, this research provides a reproducible, fine-grained energy efficiency assessment framework to advance green software engineering practices.

This study addresses the absence of open standards for CPU pipeline visualization tools and the difficulty in localizing performance bottlenecks. To this end, it proposes an open-source event stream format alongside Catscan, an interactive viewer. Methodologically, this work introduces a structured event stream based on transactional relationships, integrating typed event modeling, persistent highlighting techniques, and domain-specific search algorithms to enable microarchitectural trace analysis from symptoms down to individual instructions. Furthermore, it supports resource-oriented views synchronized with comparative trace alignment. By successfully reproducing industry-grade debugging workflows, this project provides the community with production-validated microarchitectural visualization infrastructure.

本文介绍了AmpereOne CPU核心性能验证方法，通过周期精确的相关性检查、数据驱动的工作负载管理和高频回归系统等手段，确保处理器达到性能目标。

This work addresses the lack of cost-effective, high-precision power measurement solutions for embedded systems, given the high expense and inflexibility of industrial semiconductor test equipment. The authors propose and implement a compact, open-source hardware and software-based system-level power profiling platform that integrates a Raspberry Pi controller, a high-accuracy current sensor, and a microcontroller-based device under test (DUT). A lightweight HTTP interface enables automated firmware deployment, synchronized execution, and remote control. By uniquely combining low-cost open-source hardware with an automated testing workflow, the platform achieves high-resolution current acquisition and supports energy-efficiency benchmarking and regression testing across multiple firmware variants. This significantly enhances the scalability, reproducibility, and practicality of power analysis for embedded systems, making it well-suited for research, prototyping, and educational applications.

This study addresses the challenge of optimizing server energy efficiency in high-throughput computing environments, where performance and energy consumption are often at odds. Leveraging real-world operational data and targeted experiments, the work systematically investigates how server configurations influence power consumption, performance, and carbon emissions, uncovering key barriers to implementing effective energy-saving measures in practice. Through empirical power monitoring, workload modeling, and carbon footprint assessment, the authors identify critical factors governing energy efficiency and propose a practical configuration strategy that simultaneously ensures performance guarantees and advances low-carbon objectives. Evaluated under representative high-throughput workloads, the proposed approach achieves substantial reductions in both energy use and carbon emissions.

Traditional post-layout gate-level power analysis suffers from high computational overhead and poor scalability at sub-clock-cycle granularity, hindering its applicability to efficient power delivery network design and power side-channel security assessments. This work proposes PowerScope—the first machine learning–based framework for sub-cycle power estimation—that directly predicts high-fidelity power waveforms from RTL simulation traces without requiring repeated gate-level simulations. PowerScope establishes the first end-to-end mapping from RTL to sub-cycle power consumption, achieving significant efficiency gains: it attains an average absolute percentage error of 9% (median 5.88%) across diverse benchmarks and operates approximately 80× faster than commercial tools. The framework has been successfully applied to pre-silicon evaluation of power side-channel leakage.