circuit simulation

This work addresses the critical challenge in analog and mixed-signal (AMS) circuit modeling with graph neural networks (GNNs)—the absence of publicly available, high-fidelity parasitic benchmark datasets. To bridge this gap, we introduce ParasGB, the first open-source benchmark for parasitic prediction, constructed from tape-out-validated designs and comprising large-scale heterogeneous RC networks that include node-to-ground capacitances, edge resistances, and coupling capacitances. We identify key challenges such as extreme label imbalance, long-tailed parasitic distributions, and structural heterogeneity. The project provides a unified evaluation protocol, standardized GNN training pipeline, and a fully open platform to enable early-stage parasitic estimation during pre-layout design, thereby establishing a foundation for parasitic-aware design methodologies and reproducible graph learning research in AMS circuits.

This work addresses the high simulation cost and low search efficiency in the co-optimization of SRAM architecture and transistor sizing. The authors propose the first open-source co-optimization framework that employs an equivalent circuit model to abstract inactive cells as RC loads and static power models, enabling integration of diverse optimizers—including simulated annealing, particle swarm optimization, variants of Bayesian optimization, and multi-objective evolutionary algorithms such as MOEA/D—within a unified search space. The approach achieves a 61.4× simulation speedup with timing and power errors below 0.22% and 1.68%, respectively. Among the tested methods, MOEA/D yields the best results, significantly improving static noise margin (+6.2%), substantially reducing area (−73.6%), and lowering peak power consumption (−42.3%), thereby demonstrating the complementary benefits of joint architectural and device-level optimization.

This study investigates the applicability and limitations of large language models (LLMs) in switch-mode power supply (SMPS) printed circuit board (PCB) design, with particular focus on their ability to interpret SPICE simulation results and perform multi-step, closed-loop design optimization. Method: We propose SPICEAssistant—a tool-augmented LLM framework enabling active invocation of SPICE simulators, parsing of netlists and waveform outputs, and iterative parameter refinement guided by simulation feedback. The framework supports end-to-end automation from natural-language specifications to netlist generation, simulation-driven correction, and PCB-level design convergence. Contribution/Results: Evaluated on a 256-task benchmark, SPICEAssistant achieves a 38% accuracy improvement over the GPT-4o baseline. Results demonstrate that integrating simulation-based feedback into the LLM’s reasoning loop is critical for enhancing electronic design inference, decision-making, and physical implementation fidelity.

Pre-layout SRAM simulation suffers from significant post-layout simulation mismatches and costly design iterations due to inaccurate parasitic modeling. To address this, we propose a parasitic-aware pre-layout capacitance prediction method based on a two-stage deep learning framework: (1) a graph neural network (GNN) classifier identifies highly sensitive nodes in the schematic, and (2) a multilayer perceptron (MLP) regressor predicts parasitic capacitances at those nodes. We introduce focal loss to mitigate severe class imbalance in sensitivity classification and explicitly encode hierarchical schematic topology via subcircuit-level graph structural representation. Evaluated on four industrial SRAM designs, our method reduces maximum prediction error by up to 19× and accelerates simulation by up to 598× compared to layout extraction, outperforming state-of-the-art approaches significantly.

This work addresses the insufficient modeling accuracy of multi-input gate delays in dynamic digital timing analysis. We propose the first high-fidelity hybrid delay model that jointly accounts for single-input switching (SIS) and multi-input switching (MIS), including the Charlie effect, and extend it—novelty for the first time—to CMOS multi-input gates incorporating first-order RC interconnects. The model integrates analytical formulation with SPICE validation, ensuring CMOS process portability and enabling rapid parametric evaluation. Experimental results across diverse driving strengths, wire lengths, load capacitances, and technology nodes demonstrate that our model achieves significantly lower delay prediction error than conventional models—approaching SPICE-level accuracy—while offering computational speedups of several orders of magnitude. This provides an industrially viable timing analysis solution that simultaneously delivers high accuracy and exceptional efficiency.

This study addresses the inadequacy of post-layout mapping decisions in accounting for surrounding timing constraints, fanout loads, and interconnect effects. To overcome this limitation, it proposes a local remapping framework that couples discrete search with physical feedback. The approach first isolates timing-critical regions and employs continuous relaxation to prune the search space. It then leverages mixed-integer programming to jointly optimize logic cuts, signal polarities, and library cell selection, modeling delays based on estimated placements. Finally, a closed-loop verification process encompassing legalization, routing parasitic estimation, and timing analysis is conducted to guide subsequent iterative searches. This work thereby achieves precise, physically aware, and timing-driven logic remapping.

This study addresses the limitations of existing analog circuit benchmarks in evaluating model generalization and practical usability by constructing an end-to-end benchmark comprising 273 designs derived from Tiny Tapeout open-source fabrication data. Leveraging real manufacturing data for the first time, this work establishes a containerized environment that enables precise source-code-to-SPICE mapping and training cutoff analysis. Furthermore, it incorporates automated export pipelines and graph isomorphism matching algorithms to cover schematic-to-netlist transcription and device sizing optimization tasks. Experimental results demonstrate that the best-performing model achieves a graph isomorphism accuracy of 56.1% and a sizing optimization score of 91.2. These findings reveal significant discrepancies between visual transcription and design capabilities, highlighting critical strategic bottlenecks in current models.

This work addresses the longstanding challenge in operational transconductance amplifier (OTA) design of balancing rapid analytical modeling with the high accuracy of SPICE simulation. To this end, the authors propose NEMESIS, a novel framework that uniquely integrates multimodal large language models with closed-loop SPICE simulation. By leveraging circuit primitive recognition, structure-aware automatic generation of analytical equations, and an inversion-aware mechanism, NEMESIS achieves highly efficient and accurate modeling across five OTA topologies using a 65 nm PDK. The method incorporates a SPICE-anchored refinement loop, yielding an average relative error below 7% while accelerating post-convergence evaluation by approximately 4,622× compared to full SPICE simulation.

This work addresses the insufficient reliability of large language models in low-level operations on SPICE netlists—a limitation often masked by high-level design reasoning. To rigorously evaluate structural fidelity at the netlist level, the authors introduce NetlistBench, the first benchmark dedicated to netlist structural reliability, comprising 24 task categories and 2,342 test cases. It employs a structure-aware, deterministic verifier to assess model performance on parameter identification, connectivity editing, hierarchical manipulation, and equivalence checking. The study innovatively decouples netlist-level reliability from high-level design tasks and introduces long-span composite editing challenges alongside multi-granularity evaluation strategies. Experiments reveal near-perfect accuracy (96%–100%) on simple edits, but substantial performance drops in device insertion (41%–83%) and equivalence judgment (49%–90%). While reasoning augmentation improves weaker models, maintaining structural consistency in long-span edits remains a critical bottleneck.

This study addresses the challenge that existing functional verification simulators struggle to efficiently generate large volumes of power traces under short-duration, minimally varied inputs, thereby hindering side-channel analysis during pre-silicon simulation. To overcome this limitation, this work proposes the first open-source Verilog simulator that integrates compiler-level performance, fully timed gate-level simulation, and runtime state manipulation capabilities. The tool enables multiple forked executions following a single initialization and supports pausing, inspecting, modifying, and reproducing simulation states without altering the design, thereby preserving precise timing and leakage characteristics. Experimental results demonstrate that the simulator achieves a 5.9× speedup over Icarus Verilog on an AES gate-level circuit, operates only 30% slower than Verilator while offering superior timing accuracy, and successfully recovers cryptographic keys via differential power analysis at both RTL and gate levels.