power integrity simulation

In 2.5D ICs, conventional frequency-domain impedance optimization for power delivery networks (PDNs) fails to simultaneously ensure time-domain voltage integrity due to coupling between small-signal noise and synchronous switching noise (SSN). Method: This paper proposes the first dual-domain collaborative hierarchical decoupling capacitor (decap) optimization method, integrating frequency-domain impedance modeling with time-domain transient simulation feedback within a two-stage deep reinforcement learning framework to jointly optimize decap placement across chip and silicon interposer PDNs. Contribution/Results: The method jointly minimizes impedance magnitude and time-domain voltage violation integral (VVI), achieving robust PDN design without compromising layout simplicity. Experiments demonstrate a 37% improvement in SSN suppression over conventional frequency-domain approaches, along with simultaneous reductions in both voltage violation amplitude and duration.

This study investigates the applicability and limitations of large language models (LLMs) in switch-mode power supply (SMPS) printed circuit board (PCB) design, with particular focus on their ability to interpret SPICE simulation results and perform multi-step, closed-loop design optimization. Method: We propose SPICEAssistant—a tool-augmented LLM framework enabling active invocation of SPICE simulators, parsing of netlists and waveform outputs, and iterative parameter refinement guided by simulation feedback. The framework supports end-to-end automation from natural-language specifications to netlist generation, simulation-driven correction, and PCB-level design convergence. Contribution/Results: Evaluated on a 256-task benchmark, SPICEAssistant achieves a 38% accuracy improvement over the GPT-4o baseline. Results demonstrate that integrating simulation-based feedback into the LLM’s reasoning loop is critical for enhancing electronic design inference, decision-making, and physical implementation fidelity.

This work addresses the inefficiency of traditional EDA tools in IR drop analysis for high-density chips and the limitations of existing machine learning approaches, which struggle to capture both local and long-range dependencies while neglecting layout geometry and circuit topology. To overcome these challenges, the authors propose GIF, a novel framework that jointly models geometry-aware spatial images and logical circuit graphs for the first time. GIF employs a multimodal conditional diffusion mechanism to generate high-fidelity IR drop maps. Through image-graph fused feature extraction and conditional diffusion generation, the method achieves state-of-the-art performance on the CircuitNet-N28 dataset, yielding 0.78 SSIM, 0.95 Pearson correlation coefficient, 21.77 PSNR, and 0.026 NMAE—significantly outperforming existing solutions and establishing new benchmarks in both accuracy and physical consistency.

This paper addresses scalability, memory constraints, and multi-physics coupling challenges in solving full-chip sparse linear systems ($Ax = b$) with up to $10^{10}$ unknowns in electronic design automation (EDA). It systematically surveys and comparatively analyzes three mainstream paradigms: direct methods (LU/Cholesky factorization), Krylov subspace iterative methods (CG, GMRES, BiCGSTAB), and multigrid methods (geometric and algebraic). For the first time, it unifies the analysis of their performance trade-offs under dynamic matrix updates, heterogeneous parallelism (GPU/MPI/OpenMP), mixed-precision arithmetic (FP32/FP64), and integration with multi-physics simulations (e.g., power integrity, electro-thermal coupling). Quantitative bounds are established for time complexity ($O(N)$–$O(N^2)$), memory footprint, convergence robustness, and parallel scalability. Based on this analysis, the paper proposes a practical solver selection framework and implementation guidelines tailored to industrial-scale EDA tools.

Congestion in VLSI placement is typically identifiable only after detailed routing, rendering conventional validation workflows time-consuming and costly. This work proposes VeriHGN, a novel framework that for the first time deeply integrates the logical connectivity of circuit netlists with physical placement grids into a unified, enhanced heterogeneous graph representation, overcoming the limitations of prior loosely coupled modeling approaches. Leveraging a heterogeneous graph neural network, the method achieves state-of-the-art performance on industrial benchmarks—including ISPD2015, CircuitNet-N14, and CircuitNet-N28—demonstrating superior accuracy and correlation in early-stage congestion prediction compared to existing techniques.

This work addresses the non-uniform effective resistance distribution and severe IR drop in 3D IC power delivery networks caused by suboptimal through-silicon via (TSV) placement. To enable rapid assessment of TSV layout impact on power integrity during early design stages, the authors propose a GPU-accelerated effective resistance analysis framework. Leveraging highly efficient GPU-parallelized numerical solvers as a replacement for conventional direct solvers, the method achieves a speedup of five to six orders of magnitude while maintaining exceptionally low maximum and average relative errors. Compared to traditional approaches, the proposed framework enhances analysis throughput by 10⁵–10⁶ times without compromising accuracy, thereby significantly improving the efficiency and scalability of early-stage verification for complex 3D IC power networks.

This work addresses the inefficiency and resource over-provisioning inherent in traditional power delivery network (PDN) design, which relies on worst-case assumptions. We propose a workload-aware adaptive PDN optimization framework that generates architecture-level power traces via system-level simulation and maps them into spatial density distributions. By integrating SPICE analysis with electromigration (EM) lifetime assessment, a Deep Q-Network (DQN) dynamically optimizes wire widths to minimize routing area. Evaluated on PARSEC and SPLASH-2 benchmarks, the proposed method reduces PDN area by 47% on average while satisfying EM and IR-drop constraints. Furthermore, it achieves an approximately 26× speedup in optimization time compared to simulated annealing. This approach enables efficient, workload-driven PDN resource allocation, significantly improving upon conventional conservative design methodologies.

This work addresses the limited adaptability of traditional signal integrity surrogate models, which rely on fixed buffer parameters and require repeated retraining to accommodate process and operating condition variations. The authors propose the first surrogate model that explicitly embeds dynamic buffer characteristics—such as voltage, frequency, and edge rate—into the input alongside PCB parameters, enabling cross-process generalization without retraining and supporting predictions across multiple technology nodes. A comprehensive evaluation of random forest regression, gradient boosting machines, support vector regression, kernel ridge regression, Gaussian process regression, and neural networks is conducted in a 44-dimensional design space, revealing that neural networks significantly outperform other methods in large-data regimes. When applied to eye diagram template compliance checking, the model achieves an order-of-magnitude speedup over conventional simulation while demonstrating strong engineering practicality and generalization capability.

This work addresses the critical challenge in analog and mixed-signal (AMS) circuit modeling with graph neural networks (GNNs)—the absence of publicly available, high-fidelity parasitic benchmark datasets. To bridge this gap, we introduce ParasGB, the first open-source benchmark for parasitic prediction, constructed from tape-out-validated designs and comprising large-scale heterogeneous RC networks that include node-to-ground capacitances, edge resistances, and coupling capacitances. We identify key challenges such as extreme label imbalance, long-tailed parasitic distributions, and structural heterogeneity. The project provides a unified evaluation protocol, standardized GNN training pipeline, and a fully open platform to enable early-stage parasitic estimation during pre-layout design, thereby establishing a foundation for parasitic-aware design methodologies and reproducible graph learning research in AMS circuits.

This study addresses the challenge of satisfying quantitative electromagnetic specifications when applying diffusion models to PCB inverse design. To this end, it proposes Simulation-guided Reverse Diffusion (SRD), a method whose core innovation lies in integrating a low-fidelity differentiable surrogate with a high-fidelity non-differentiable full-wave simulator to optimize the sampling process. Specifically, gradients from the surrogate model provide directional guidance, while the simulator performs precise searches along these directions to update samples, replacing conventional stochastic perturbation strategies. Experimental results demonstrate that SRD improves S-parameter matching accuracy by approximately 21.2% compared to state-of-the-art methods. This work establishes a new paradigm for generative design under physical constraints.