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Designs, builds, and analyzes electrical power delivery networks and architectures that route, distribute, and regulate supply voltages from sources to loads across a device or system, including grids, circuits, and distribution systems (e.g., on‑chip/backside, package, and board‑level implementations). Work includes selecting and sizing conductors and components, defining topology and layout, and evaluating voltage/IR drop, current density, transient response, thermal limits, and reliability of the power distribution.
本文针对高密度和引脚数瓶颈导致的供电难题,提出设计多级分布式供电系统的方法,以支持复杂3D异构集成系统的可靠电力供应。
本文探讨了AI数据中心作为电网交互计算系统的技术视角,通过工作负载调度、冷却系统等方法解决能源可用性和电网连接容量的问题。
This work addresses the inefficiency and resource over-provisioning inherent in traditional power delivery network (PDN) design, which relies on worst-case assumptions. We propose a workload-aware adaptive PDN optimization framework that generates architecture-level power traces via system-level simulation and maps them into spatial density distributions. By integrating SPICE analysis with electromigration (EM) lifetime assessment, a Deep Q-Network (DQN) dynamically optimizes wire widths to minimize routing area. Evaluated on PARSEC and SPLASH-2 benchmarks, the proposed method reduces PDN area by 47% on average while satisfying EM and IR-drop constraints. Furthermore, it achieves an approximately 26× speedup in optimization time compared to simulated annealing. This approach enables efficient, workload-driven PDN resource allocation, significantly improving upon conventional conservative design methodologies.
This work addresses the inefficiencies of traditional early-stage power delivery network (PDN) design, which relies on static or worst-case power assumptions and often leads to over-provisioning of resources and suboptimal routing. The authors propose a workload-aware PDN optimization methodology that, for the first time at the architectural level, incorporates real application-driven dynamic power traces. By performing fine-grained temporal power simulations, the approach generates spatiotemporal power density maps and translates them into current demand profiles to guide tile-level PDN topology planning. This enables adaptive resource allocation aligned with actual application behavior, achieving up to a 32.94% reduction in PDN metal area compared to conventional designs while satisfying IR drop and electromigration constraints.
To address data transmission unreliability in Network-on-Chip (NoC) systems induced by power supply noise (PSN), this paper proposes a modular modeling and probabilistic verification methodology based on the Modest language. The method integrates modular router models with a hierarchical verification framework, enabling unified formal verification of functional correctness and PSN sensitivity—from individual routers up to 8×8 NoC topologies. Leveraging the Modest Toolset, we perform rigorous formal verification and statistical model checking to quantitatively assess communication consistency, functional reliability, and noise robustness. Compared to conventional approaches, our methodology significantly enhances verifiability, scalability, and model reusability at early design stages. It establishes a novel, formally grounded modeling paradigm for high-reliability NoC design under heterogeneous and dynamic traffic conditions.
This study addresses the scarcity of realistic distribution network datasets—a key bottleneck in benchmarking planning and operational tools under high penetration of distributed energy resources. To overcome this, the authors propose a generative adversarial network (GAN)-based framework for synthesizing distribution grid layouts, uniquely integrating rasterized image representations with GANs to enable both unconditional generation and geographically conditioned synthesis incorporating street maps and customer distribution. Through GIS preprocessing, image-based topological encoding, and a multi-resolution training strategy, the method successfully reproduces realistic topologies aligned with geographic structures across low-, medium-, and high-voltage scenarios. The approach offers data-driven layout recommendations for electrifying new areas while also highlighting persistent challenges in training stability and modeling electrical constraints.
This work addresses the lack of systematic educational resources in high-performance computing (HPC) networking, which poses a significant barrier for researchers entering the field. It presents the first comprehensive integration of the HPC networking stack, covering communication protocol layers, programming interfaces such as MPI, control plane mechanisms, high-speed interconnect technologies, and custom link-layer hardware. The exposition is anchored by a detailed case study of the El Capitan supercomputer architecture at Lawrence Livermore National Laboratory. By offering a well-structured, practice-oriented primer, this contribution fills a critical educational gap and substantially lowers the entry barrier for researchers seeking to master core HPC networking technologies.
This work addresses the challenges in advanced packaging posed by high-density redistribution layers, where congestion in fanout regions is difficult to model accurately and existing pin assignment methods struggle to mitigate net crossings. To tackle these issues, the paper introduces, for the first time, differentiable optimization into the co-design of package placement and pin assignment, proposing an end-to-end joint optimization framework. This framework integrates a differentiable wirelength model with a fanout-aware congestion estimator, a gradient back-propagation mechanism for discrete die orientations, and a crossing-aware pin assignment strategy, all accelerated by a GPU-enhanced multi-strategy DPSO algorithm. Evaluated across all benchmark cases, the approach achieves 100% routability, with successful instances demonstrating up to a 23% reduction in wirelength compared to state-of-the-art baselines.
This study addresses the challenges of heterogeneous, sparse data and cross-network generalization in power distribution grids by proposing Mycelium, a heterogeneous graph Transformer. Methodologically, the authors construct a unified grid ontology and a physics-based simulation pipeline to generate high-quality training data. The model introduces structure-aware communication edges and electrical reference feature encoding, integrated with task-specific temporal readout mechanisms, to enable physics-driven, cross-grid universal representation learning. Experimental results demonstrate that Mycelium surpasses specialized baselines on unseen benchmark networks, substantially improving multi-task inference performance and cross-domain generalization capabilities.
This study addresses the Distribution Network Reconfiguration (DNR) problem, which seeks to minimize resistive power losses under radial topology constraints. Combining combinatorial optimization, approximation algorithm design, and complexity theory, the work establishes several key results for both single- and multi-feeder settings. It proves for the first time that DNR admits no $n^{1-\varepsilon}$-approximation algorithm even on planar graphs unless P = NP. For the single-feeder case, the paper presents an $O(\sqrt{n})$-approximation algorithm and establishes its APX-hardness, resolving an open question posed by Gupta et al. In the two-feeder setting, it derives an $\Omega(\log^2 n)$ lower bound on approximability and provides a general $n$-approximation algorithm applicable to arbitrary numbers of feeders.