parasitic extraction

Existing methods for converting circuit schematic images into EDA-processable netlists suffer from poor generalizability across IC and PCB domains, inaccurate component recognition, ambiguous connectivity inference, and frequent misinterpretation of crossing wires. This work proposes the first fully automated parsing pipeline that integrates deep learning, connected-component labeling, OCR, and vision-language models to precisely extract components, labels, and topological connections. A dedicated crossing-wire detection module is introduced to distinguish genuine electrical junctions from mere graphical overlaps. The approach unifies processing for both IC and PCB schematics and achieves a netlist accuracy of 96.67% on real-world datasets—2.72 times higher than the current state-of-the-art—while ensuring functional equivalence through graph isomorphism verification.

Congestion in VLSI placement is typically identifiable only after detailed routing, rendering conventional validation workflows time-consuming and costly. This work proposes VeriHGN, a novel framework that for the first time deeply integrates the logical connectivity of circuit netlists with physical placement grids into a unified, enhanced heterogeneous graph representation, overcoming the limitations of prior loosely coupled modeling approaches. Leveraging a heterogeneous graph neural network, the method achieves state-of-the-art performance on industrial benchmarks—including ISPD2015, CircuitNet-N14, and CircuitNet-N28—demonstrating superior accuracy and correlation in early-stage congestion prediction compared to existing techniques.

Existing machine learning approaches struggle to generate manufacturable RF GDSII layouts due to oversimplified component models and the absence of routing capabilities. This work proposes the first machine learning–driven physical synthesis framework tailored for RF circuits, integrating a high-fidelity neural inductor model trained on 18,210 structures and 7.5 million samples, a DRC-aware intelligent P-Cell optimizer, and a placement-and-routing engine that enforces frequency-dependent electromagnetic spacing rules. The framework enables co-optimization of electromagnetic awareness and design rule compliance. Experimental results demonstrate inductor Q-factor prediction errors below 2%, a 93.77% success rate in generating high-Q layouts, and successful production of DRC-clean GDSII outputs, with real-time inference support across the 1–100 GHz range.

Existing methods for converting SPICE netlists into human-readable schematics lack guarantees of connectivity correctness and suffer from significantly degraded accuracy as circuit complexity increases. This work proposes a deterministic conversion approach based on Sugiyama’s layered graph layout, integrating an embedded pinout database of 5,093 LTspice symbols and a round-trip connectivity verification mechanism. For the first time, this method enables netlist-to-schematic translation with a binary correctness certificate, ensuring network-by-network equivalence between the generated schematic and the original netlist. Implemented as a client-side, single-file, dependency-free architecture, the approach achieves 100% compilation success and connectivity verification pass rates on the Circuits-LTSpice benchmark and demonstrates an 88.4% verification pass rate on Analog Devices’ official dataset of 3,460 circuits.

Existing circuit representation learning methods rely heavily on graph models tailored for simple And-Inverter Graphs (AIGs), limiting their capacity to capture complex gate-level semantics; while large language models (LLMs) excel at functional understanding, they lack native awareness of netlist structural topology. This work introduces the first netlist foundation model for integrated circuit design. We propose a novel Text-Annotated Graph (TAG) representation that unifies logical expressions and physical attributes as gate-level textual features. Furthermore, we design an RTL-to-layout co-aligned multi-task self-supervised pretraining paradigm, integrating an LLM-based text encoder with a graph Transformer to jointly optimize semantic comprehension, structural learning, and cross-stage alignment. Evaluated on four functional and physical IC design tasks—including logic optimization, timing prediction, placement, and routing—the model consistently outperforms task-specific baselines and state-of-the-art AIG encoders, demonstrating superior representational generality and cross-task transferability.

This work addresses the critical challenge in analog and mixed-signal (AMS) circuit modeling with graph neural networks (GNNs)—the absence of publicly available, high-fidelity parasitic benchmark datasets. To bridge this gap, we introduce ParasGB, the first open-source benchmark for parasitic prediction, constructed from tape-out-validated designs and comprising large-scale heterogeneous RC networks that include node-to-ground capacitances, edge resistances, and coupling capacitances. We identify key challenges such as extreme label imbalance, long-tailed parasitic distributions, and structural heterogeneity. The project provides a unified evaluation protocol, standardized GNN training pipeline, and a fully open platform to enable early-stage parasitic estimation during pre-layout design, thereby establishing a foundation for parasitic-aware design methodologies and reproducible graph learning research in AMS circuits.

This work addresses the insufficient reliability of large language models in low-level operations on SPICE netlists—a limitation often masked by high-level design reasoning. To rigorously evaluate structural fidelity at the netlist level, the authors introduce NetlistBench, the first benchmark dedicated to netlist structural reliability, comprising 24 task categories and 2,342 test cases. It employs a structure-aware, deterministic verifier to assess model performance on parameter identification, connectivity editing, hierarchical manipulation, and equivalence checking. The study innovatively decouples netlist-level reliability from high-level design tasks and introduces long-span composite editing challenges alongside multi-granularity evaluation strategies. Experiments reveal near-perfect accuracy (96%–100%) on simple edits, but substantial performance drops in device insertion (41%–83%) and equivalence judgment (49%–90%). While reasoning augmentation improves weaker models, maintaining structural consistency in long-span edits remains a critical bottleneck.

为解决AI驱动的PCB设计自动化中缺乏大规模配对数据集的问题，通过构建包含300多个实际设计的PCBnet数据集，并开发自动化的原理图到网表转换流程。

This work addresses the challenge that existing large language models struggle to simultaneously satisfy stringent geometric, routing, and electrical connectivity constraints in dense PCB layout design. To bridge this gap, we introduce OmniLayout, the first multimodal benchmark specifically tailored for PCB layout, which jointly models schematic diagrams and physical layouts. The benchmark encompasses four constraint-aware reasoning tasks designed to systematically evaluate model capabilities in geometric reasoning, routability, preservation of electrical functionality, and tool invocation. Integrating industrial-scale layout data, geometric constraint modeling, routing analysis, and circuit verification, our framework exposes critical limitations of current models—particularly their weak geometric reasoning, poor routing optimization, and insufficient functional consistency—thereby filling a crucial void in evaluating multimodal collaborative reasoning within electronic design automation.

This work addresses the longstanding challenge in operational transconductance amplifier (OTA) design of balancing rapid analytical modeling with the high accuracy of SPICE simulation. To this end, the authors propose NEMESIS, a novel framework that uniquely integrates multimodal large language models with closed-loop SPICE simulation. By leveraging circuit primitive recognition, structure-aware automatic generation of analytical equations, and an inversion-aware mechanism, NEMESIS achieves highly efficient and accurate modeling across five OTA topologies using a 65 nm PDK. The method incorporates a SPICE-anchored refinement loop, yielding an average relative error below 7% while accelerating post-convergence evaluation by approximately 4,622× compared to full SPICE simulation.