intent-to-topology synthesis

This work addresses the core challenge in network automation: automatically generating deployable network topologies from natural language requirements while satisfying structural and resilience constraints. We propose a large language model (LLM)-based, constraint-driven framework that translates natural language into compliant topologies through hierarchical intent parsing and systematic validation. To facilitate evaluation, we introduce the first benchmark for this task, releasing a public dataset encompassing four real-world scenarios and characterizing common generation error patterns. Extensive experiments across multiple proprietary and open-source LLMs demonstrate the framework’s effectiveness, with performance quantified using metrics including topological correctness, node/edge F1 scores, and server-content connectivity. Our results provide actionable guidance for model selection in AI-driven network design.

This work addresses the challenge of automatically translating unstructured natural language security requirements into compliant, executable network topologies. It presents the first end-to-end framework that compiles ambiguous security intents into network architectures adhering to CIS Controls v8.1.2. The approach leverages schema contracts to constrain intent semantics, employs dense vector retrieval to match reference architectures, and fuses user intent with templates in a staged manner, followed by structure-preserving incremental editing to complete security policies. The system supports human-in-the-loop validation for uncovered scenarios and exports configurations for Mininet and iptables. Evaluated on financial and governmental test sets, the framework achieves full CIS compliance—raising topology compliance from 0.78 to 1.00—with an average of only 1.5 refinement rounds, while access control list (ACL) policies attain a one-round feedback pass rate of 0.88.

In enterprise network engineering, physical topology modifications and device configuration updates have long relied on error-prone, inefficient manual processes; existing automation research predominantly focuses on configuration synthesis while neglecting co-evolution with topology changes. This paper proposes the first intent-driven, closed-loop automation framework tailored for enterprise networks. It integrates multimodal large language models (MLLMs), optical character recognition (OCR), and a graph-structure-aware visual encoder to jointly understand topology diagrams and textual intent specifications. We introduce a novel topology–configuration co-prompting engineering paradigm and a Cisco-certified scenario fine-tuning mechanism. Evaluated on real-world enterprise deployments, our framework achieves significantly improved topology image parsing accuracy, reduces network design cycle time by over 40%, and attains an 89.2% execution accuracy for topology-modification intents—substantially decreasing manual intervention.

Analog circuit topology synthesis faces two key challenges: existing methods rely on imprecise specifications, neglect engineering constraints, and oversimplify design as graph or code generation—divorcing it from real expert decision-making. This paper introduces the first practical, LLM-driven topology synthesis framework: it embeds domain expertise into large language models, leverages a measured SPICE subcircuit library as primitives, and performs end-to-end topology generation via stepwise block selection, interconnection, chain-of-thought guidance, and iterative SPICE-level validation and correction. Key contributions include: (1) the first formalization of authentic analog design workflow as an LLM agent behavior; (2) construction of the first high-quality benchmark comprising 30 measured circuit cases; and (3) introduction of SPICE-native representation and subcircuit-constrained search. Our method achieves 40% success rate on synthetic data and 23% on real-world data—substantially outperforming GPT-4o (3% and 3%, respectively).

Software engineers face significant challenges—including difficulty in modeling, lengthy prototyping cycles, and high verification costs—when developing control algorithms for complex dynamic systems such as communication networks. To address these issues, we propose GIPS, the first model-driven engineering framework that tightly integrates graph-structured integer linear programming (ILP) modeling with automated code generation. Using the domain-specific language GIPSL, users declaratively specify constraints and optimization objectives; GIPS then automatically generates functionally complete, executable Java graph-optimization components. This enables end-to-end rapid prototyping—from high-level specifications to runtime deployment. We validate GIPS on a tree-structured peer-to-peer topology control scenario, demonstrating its correctness, efficiency, and scalability. The full implementation—including source code and a ready-to-run virtual machine demonstration environment—is open-sourced, confirming its practical deployability and engineering utility.

Current prompt graphs lack a clear definition and standardized terminology, resulting in conceptual ambiguity in practice. This work addresses this gap by proposing a formal definition of prompt graph engineering through conceptual analysis, gray literature review, and systematic categorization. It identifies prompt graphs as first-class, executable, and improvable engineering artifacts and establishes four necessary constitutive conditions along with inclusion and exclusion criteria for operational validation. The proposed definition demonstrates consistent applicability across six major frameworks—including LangGraph and DSPy—thereby offering the field its first operational framework and shared vocabulary. Building on this foundation, the paper outlines a future research agenda structured around four key design tensions inherent to prompt graph development.

This work addresses the ongoing challenge of automatically translating natural language specifications into editable printed circuit board (PCB) schematics for embedded and IoT development. It presents the first end-to-end approach that leverages tool-augmented large language model reasoning, integrating component library retrieval, datasheet knowledge extraction, execution validation, and structural-semantic verification to generate KiCad-compliant schematics. The system supports iterative refinement through an interactive web interface and achieves a pass@1 rate of 0.90 and a pass@5 rate of 1.00 across 20 embedded schematic generation tasks. This method efficiently produces high-quality initial drafts suitable for early-stage prototype review, substantially advancing the state of hardware design automation.

This work addresses the challenge of simultaneously preserving visual layout, editable structure, and semantic consistency when editing software diagrams via natural language. The authors propose a structured agent-based diagram editing paradigm that models diagrams as editable graph structures, parses natural language instructions into structured editing intents, and translates these into sequences of graph operations. This approach enables semantics-preserving editing for both Draw.io and Mermaid formats by integrating state management with model-driven interpretation, and combines direct canvas manipulation with masked image editing to support recoverable, versioned workflows. Evaluation on a Kubernetes architecture case study demonstrates advantages in structural validity, editing success rate, and preservation of irrelevant elements, while unit tests provide insight into failure modes.