parallel interleave decoding

This work addresses the inherent trade-off in fixed-window decoding for quantum error correction, where a static decoding window introduces latency that impedes both low reaction time and target logical error rates. To overcome this limitation, the authors propose an adaptive window decoding scheme that dynamically adjusts the decoding window size based on the decoder’s confidence level—a novel application of confidence estimation in this context. By integrating this approach with various quantum error-correcting codes under hardware-inspired noise models, the method maintains the desired logical error rate while significantly reducing average decoding latency. Experimental results demonstrate consistent reductions in time overhead across diverse code families and noise configurations, thereby surpassing the efficiency constraints of conventional fixed-window strategies.

This work addresses the conflation in existing parallel decoding research between algorithmic token utilization and actual system overhead, which obscures an accurate characterization of “near-zero additional latency” parallelism. The paper introduces the concept of Near-Free Parallelism (NFP), explicitly distinguishing algorithmic parallelism from system costs for the first time. By analyzing the behavior of dense feedforward networks, Mixture-of-Experts (MoE), and attention mechanisms under an idle-compute baseline, it reveals that NFP is jointly constrained by memory resource slack and kernel granularity. Leveraging hardware resource balancing and kernel-granularity-aware evaluation, the study establishes a predictive criterion for NFP boundaries, correcting traditional idle-compute intuition that can overestimate NFP by up to 23×. Empirical validation across diverse dense and MoE models in both diffusion and autoregressive decoding tasks confirms the accuracy of this framework, offering a reliable system-side budgeting foundation for parallel strategy selection and model-system co-design.

In fault-tolerant quantum computing (FTQC), classical decoders for quantum error correction (QEC) face severe resource demand fluctuations—peak loads can exceed idle-period requirements by several orders of magnitude—rendering static hardware allocation inefficient (causing underutilization or real-time violations). Method: We propose the first workload-aware decoder virtualization framework and latency-aware dynamic scheduling strategy, enabling elastic, on-demand allocation of hardware decoder resources. Our approach integrates fine-grained syndrome processing modeling, reusable customized decoder designs, and cross-logical-qubit task coordination. Contribution/Results: Evaluated at the 100–1,000 logical qubit scale, our method reduces hardware decoder resource requirements by 10× while strictly guaranteeing real-time decoding latency and fault-tolerance reliability. This breakthrough overcomes a critical scalability bottleneck in the classical processing layer of QEC, providing essential infrastructure for practical FTQC deployment.

This work addresses the real-time classical decoding challenge for multi-logical-qubit lattice surgery operations in surface-code quantum error correction. We propose a spatially parallel sliding-window decoding architecture that partitions physical qubits into overlapping subsets, each assigned a dedicated hardware decoding module to achieve high-throughput, low-latency, and high-fidelity syndrome decoding. Our approach is the first to systematically resolve the parallel decoding configuration problem for general lattice surgery under hardware resource constraints; it further reveals that buffer width must be dynamically optimized according to the physical noise rate to jointly balance decoding accuracy and throughput. Experimental evaluation demonstrates that the architecture satisfies real-time decoding requirements for full-scale, device-level merge patches while preserving logical fault tolerance—establishing a new paradigm for noise-adaptive, scalable quantum decoders.

Short LDPC codes exhibit residual errors under normalized min-sum (NMS) decoding, while conventional ordered statistics decoding (OSD) achieves high error-correction performance at prohibitively high computational complexity—rendering it unsuitable for ultra-low-latency applications. To address this trade-off, we propose a lightweight neural-enhanced OSD framework. Our method introduces: (i) a sliding-window-assisted neural network to enable early termination of OSD iterations; (ii) a bit-reliability refinement mechanism leveraging iterative failure information; and (iii) a structured, block-wise test-error pattern generation strategy. Evaluated on standardized short LDPC codes, the proposed decoder attains state-of-the-art (SOTA) bit-error-rate (BER) performance—matching or surpassing conventional OSD—while reducing average decoding latency by up to 62% and computational complexity by over 50%. The approach is particularly well-suited for ultra-reliable low-latency communication (URLLC) systems, such as those in 5G and beyond.

This study addresses the suboptimal scheduling efficiency in layered decoding of generalized low-density parity-check (GLDPC) codes by systematically analyzing how subcode structural properties affect message-passing convergence. It reveals, for the first time, a direct relationship between constraint node scheduling priority and key subcode characteristics—namely, minimum distance, number of minimum-weight codewords, and code length. Building on this insight, the paper proposes a novel scheduling strategy that prioritizes updating constraint nodes associated with subcodes exhibiting larger minimum distance, fewer minimum-weight codewords, and shorter length. Simulation results demonstrate that the proposed algorithm significantly enhances both decoding efficiency and convergence speed for GLDPC codes.

This work addresses the high computational complexity of soft-decision maximum-likelihood decoding, which typically relies on preconstructed structures such as trellises or error-pattern lists. The authors propose an efficient decoding framework that requires only the parity-check matrix, introducing a novel recursive error-building-block mechanism grounded in algebraic properties. This approach directly approximates the most likely error pattern through local optimal search without any preprocessing overhead. By integrating offline and online exclusion strategies tailored specifically for extended Hamming codes, the method substantially reduces computational cost. Experimental results demonstrate that, at a frame error rate of 10⁻³, the proposed decoder achieves approximately one order of magnitude reduction in average floating-point operations compared to the minimal-edge trellis Viterbi algorithm for extended Hamming codes of lengths 64, 128, and 256, with no loss in decoding performance.

Fault-tolerant quantum computing demands real-time surface code decoders with low latency and high throughput to bridge the gap between room-temperature control systems and cryogenic hardware. This work presents the first implementation and validation of the Snowflake streaming decoder on a commercial FPGA under cryogenic conditions, demonstrating its practical feasibility. The authors introduce a locality-aware 2D sliced parallel architecture to enable scalable deployment across large code distances and integrate a lightweight confidence scoring mechanism with near-zero overhead. Experimental results show that the design achieves high-throughput decoding at small code distances, with extrapolated performance sufficient for larger distances. Critically, the added latency and resource consumption from the confidence scoring module are negligible, preserving the decoder’s efficiency while providing valuable reliability metrics.

This work addresses the lack of a unified and parallelizable soft-decoding framework for binary linear block codes, which leads to high hardware complexity in multi-code scenarios. The paper proposes Polarized Orbit Decoding (POD), the first approach that integrates automorphism orbits with polar decoding by executing multiple equivalent decoding paths in parallel after a polarizing transformation, thereby achieving low-latency, high-performance universal soft decoding. Leveraging the Schreier–Sims algorithm, the method represents the automorphism group as a base and strong generating set (BSGS), enabling systematic offline computation in polynomial time and efficient orbit traversal without requiring refreezing or exhaustive search. Evaluated on extended BCH and Golay codes, POD attains maximum-likelihood performance while significantly outperforming conventional serial list decoding in terms of latency.

This study reveals a pronounced non-monotonic latency behavior in Apple’s Metal Performance Shaders (MPS) backend during autoregressive decoding, challenging the widely held assumption that KV caching universally improves inference efficiency. Through controlled experiments on models including GPT-2, BLOOM, and OPT, the authors systematically compare MPS against CPU and NVIDIA T4 platforms, uncovering latency spikes of up to 21× within specific decoding length ranges on MPS—phenomena unexplained by memory pressure or prefill costs. The work provides the first characterization of the discontinuous latency patterns in MPS decoding, attributing them to backend execution scheduling mechanisms. These findings underscore the critical importance of hardware-aware evaluation for inference optimization and caution that aggregate benchmarking metrics may obscure such pivotal performance anomalies.