model checking

Verifying low-level system software (e.g., OS kernels, device drivers) requires unified modeling of hardware-awareness, concurrency, and memory safety—properties that are notoriously difficult to capture coherently within a single formal framework. Method: This paper proposes a resource-contextual modal logic verification paradigm. It systematically identifies and formalizes modal verification design patterns, embedding resource constraints—such as memory regions, lock states, and device register configurations—directly into the semantics of modal operators. This enables structured, compositional specification and verification of system-level behaviors. Contribution/Results: We establish the first reusable modal modeling paradigm tailored to systems software, bridging the gap between modal logic theory and systems engineering practice. Evaluated on multiple real-world case studies, our approach demonstrates strong effectiveness and scalability, significantly enhancing both specification expressivity and verification automation.

Theorem provers exhibit unstable performance, poor scalability, and low reproducibility in behavioral verification—particularly for real-time and safety-critical software. Method: We systematically reproduce and extend existing benchmarks to construct an empirical evaluation framework featuring diverse behavioral models and logical specifications, enabling rigorous assessment of robustness, scalability, and reproducibility across mainstream theorem provers. Contribution/Results: Our study is the first to empirically establish strong correlations between irregular solver performance and structural problem characteristics—specifically temporal constraint density and state-space distribution. Leveraging these insights, we propose adaptive heuristic strategies and a self-optimizing solver architecture. The approach delivers measurable stability improvements for just-in-time verification in CI/CD pipelines and AI-augmented IDEs, significantly enhancing the practicality and trustworthiness of automated logical verification in high-assurance software development.

This work addresses the challenges of model uncertainty and unpredictability in partially observable or black-box systems during runtime by proposing a unified theoretical framework that integrates epistemic logic with temporal logic. Leveraging automata theory, it systematically formalizes core concepts—including specification, diagnosis, opacity, and monitorability—and synthesizes lightweight online monitors through offline analysis. The approach is extended to real-time systems, resolving key issues related to their temporal semantics and algorithmic complexity. Furthermore, the study precisely characterizes the fundamental limits of runtime verification, thereby establishing a constructive and implementable foundation for practical deployment of monitoring mechanisms.

Natural language requirements are ill-suited for direct use in formal verification. Method: This work proposes an automated property generation framework integrating large language models (LLMs) with formal verification tools. It introduces an assertion generation mechanism extending beyond Linear Temporal Logic (LTL) to support numerical constraints and compositional system behavior modeling; integrates Claude 3.5 Sonnet with the ESBMC bounded model checker; and employs human-in-the-loop supervision to calibrate output quality. Contribution/Results: We first identify and characterize systematic impacts of LLM-induced model connection errors and numerical approximations on verification outcomes—reducing false positives and uncovering previously overlooked falsifiable scenarios. Evaluated on nine cyber-physical systems from Lockheed Martin, our approach achieves 46.5% verification accuracy—on par with NASA’s CoCoSim—while substantially lowering the barrier to formal verification and enhancing defect detection capability.

This paper addresses hyperproperties—higher-order system requirements encompassing information-flow security, knowledge reasoning, and robustness, which span multiple execution traces—by proposing the first unified logical and algorithmic framework covering the entire verification lifecycle. Methodologically, it rigorously characterizes the expressive power and decidability boundaries of classical temporal logics (LTL, CTL, S1S) over hyperproperties; then introduces a novel multi-trace synchronization modeling and quantifier alternation handling mechanism grounded in higher-order temporal logic, constraint solving, and symbolic automata. Key contributions include: (i) a comprehensive taxonomy and complexity-theoretic characterization of hyperproperty logics; (ii) an open-source verification toolchain supporting HyperLTL and HyperCTL*; and (iii) end-to-end support for core verification tasks—including satisfiability checking, model checking, runtime monitoring, and controller synthesis.

This study addresses the limitations of existing SysML verification approaches, which are often tool-dependent and restricted to performance properties, lacking support for automated validation of behavioral and interface requirements. To overcome these shortcomings, this work proposes a tool-agnostic, automated verification workflow driven by SysML test cases, integrating UML Testing Profile and behavioral diagram constructs to enable unified validation of multidimensional attributes—including behavior, timing, and state responses. The methodology was developed through a mixed-methods research strategy combining literature review and stakeholder interviews, and its efficacy was empirically validated across two independent SysML toolchains. The approach not only transcends the constraints of conventional parametric methods but also enables automatic traceability of verification results back to the original model elements.

Standard simulation techniques struggle to verify liveness properties, and existing notions of fair simulation are often too complex for interactive verification. This work proposes a family of “approximate fair simulation” relations tailored to transition systems equipped with Büchi fairness conditions. By simplifying the nested inductive–coinductive structures inherent in traditional approaches, our method introduces a stronger and more user-friendly reasoning mechanism. We formalize this framework within a fixed-point logic and develop a corresponding deductive system, which we mechanize and prove correct in the Rocq proof assistant. Case studies demonstrate the effectiveness and practicality of our approach for interactive verification of fairness properties.

This work addresses the challenge of ensuring safety, reliability, and trustworthiness in collective adaptive systems operating in dynamic environments by proposing a modular design paradigm centered on intrinsic trustworthiness. The approach integrates a runtime model based on local causal event sequences, a temporal logic verification technique supporting modular architectures, and a compositional reasoning mechanism for global system properties grounded in component attributes. Through this tripartite framework, the study overcomes key limitations of conventional formal methods and demonstrates substantial improvements in verifiability and scalability in case studies, thereby establishing both a theoretical foundation and a practical pathway for engineering highly trustworthy collective adaptive systems.

This work addresses the lack of theoretical characterization in large-scale labeled transition systems (LTS), which has hindered the principled design of heuristics in model checking. For the first time, we systematically apply random graph theory to construct a probabilistic model of large-scale LTS with realistic parameters and analyze its asymptotic behavior under both LTL and CTL logics. We establish convergence properties—specifically, 0–1 laws—for the satisfaction probability of logical formulas and develop efficient algorithms to compute the corresponding limiting probabilities. Our results provide a rigorous theoretical foundation for heuristic strategies in model checking and fill a critical gap in the formal analysis of large-scale LTS.

This work addresses the challenge that counterexamples generated by formal verification often consist of numerous low-level Boolean variables, rendering them difficult for developers to interpret at the application-domain level. To bridge this gap, the paper proposes a novel hierarchical explanation method that integrates predicate relevance metrics with dependency graph analysis—a first-time fusion of these two techniques—to automatically extract human-readable, domain-oriented explanations from logical formulas. By leveraging formal modeling and a dedicated explanation-generation algorithm, the approach produces concise and semantically clear descriptions of failure causes across multiple case studies. Empirical results demonstrate that the method significantly outperforms existing techniques, offering effective support for fault localization in practical verification tasks.