out-of-core processing

This work addresses memory exhaustion and I/O bottlenecks in processing petabyte-scale image datasets—such as 1.4 PB electron microscopy volumes or 150 TB organ atlases—by introducing a streaming single-pass architecture based on a sweep execution model. The approach aligns disk reads with a one-dimensional sweep order and combines windowed operations with overlap-aware tiling to enable efficient processing under tight memory constraints. A domain-specific language (DSL) is designed to automatically optimize window sizes, fuse pipeline stages, and schedule multi-pass sweeps at compile time and runtime. The system supports Zarr, HDF5, and slice-based formats without requiring full-image residency in memory, achieving significantly higher throughput, near-linear I/O scaling, and predictable memory usage while seamlessly integrating with existing segmentation and morphological analysis toolchains.

To address CPU bottlenecks in data preprocessing, imbalanced resource allocation, and insufficient fault tolerance during ML training and inference on CPU-GPU heterogeneous systems, this paper proposes a Streaming-Batch hybrid execution model. It synergistically integrates the low-latency benefits of streaming execution with the high-throughput advantages of batched processing, enabling shard-wise incremental execution, lineage-based lightweight fault recovery, and dynamic heterogeneous resource scheduling—thereby eliminating reliance on homogeneous hardware. Implemented atop Ray Data, the model achieves 3–8× higher throughput for heterogeneous batch inference. In Stable Diffusion training, it improves end-to-end training throughput by 31% while preserving per-node data loading throughput.

To address low cross-facility transfer efficiency and high integrity verification overhead for terabyte-scale files in exascale computing environments, this paper proposes a client-driven dynamic chunking mechanism, the first of its kind to be deeply integrated into the Globus platform. Methodologically, it synergistically combines automated chunking scheduling, parallel transfer optimization, and incremental hash-based integrity verification—departing from conventional small-file-centric transfer optimization paradigms. Experimental evaluation demonstrates up to a 3.2× improvement in end-to-end throughput for TB-scale file transfers and an 87% reduction in integrity verification latency compared to baseline approaches. The solution has been deployed and validated across multiple national flagship supercomputing facilities, significantly enhancing performance, reliability, and scalability for large-scale scientific data movement.

To address the dual challenges of I/O bottlenecks and catastrophic forgetting in large-scale plasma simulations, this work introduces the Streaming AI Scientist framework, which pioneers an *in-transit* machine learning paradigm featuring tight simulation–learning coupling. It bypasses filesystem I/O via zero-copy in-memory data streaming, enabling real-time co-execution of simulation and ML training. An asynchronous feature transformation pipeline and an experience-replay–based continual learning mechanism mitigate catastrophic forgetting in non-stationary physical processes. The framework supports cross-language, zero-modification integration with existing simulation codes. Technically, it integrates GPU acceleration (PIConGPU), streaming pipelines, asynchronous memory transfers, and Frontier exascale supercomputer optimization. Evaluated on a thousand-GPU Kelvin–Helmholtz instability workflow on Frontier, it reduces I/O overhead by 90%, achieves storage-free, sub-second model updates, and enables online physical pattern recognition.

To address the on-chip memory bandwidth bottleneck in AI/ML streaming applications—exacerbated by growing model and data sizes, especially under data-parallel architectures (e.g., GPUs, neural accelerators) and low-data-reuse loop nests—this work proposes a scalable three-level heterogeneous on-chip memory hierarchy (local/intermediate/global), integrating ultra-wide register files and a programmable data rearranger. It further introduces customized data mapping and memory access scheduling algorithms tailored for streaming workloads such as CNNs. The key innovations are the first scalable three-level on-chip memory architecture and a dynamic data rearrangement mechanism, significantly enhancing vector processors’ adaptability to diverse data reuse patterns. Evaluated on representative CNN workloads, the design achieves up to a 2.3× improvement in memory bandwidth utilization over GPU and systolic-array baselines, along with a 41% gain in end-to-end energy efficiency and a 36% reduction in latency.

This study addresses the low GPU utilization and irreproducibility commonly encountered in large-scale distributed GPU training due to data loading bottlenecks. Through a systematic analysis of I/O and CPU constraints, the authors propose an optimized architecture that integrates push-based worker transformation with local disk caching. They design a Fanout-Cache mechanism and a dedicated polling queue to eliminate race conditions arising from multi-process shared queues, and incorporate deterministic random number generation to ensure strict reproducibility in high-throughput data pipelines—a first in this context. Leveraging optimizations based on Petastorm, Parquet, and PyArrow-to-NumPy conversions, the approach reduces end-to-end training time from 22 hours to 3 hours (a 6× speedup), increases GPU utilization to over 60%, and substantially decreases inter-run variance.

This work addresses the performance limitations of data-intensive applications in edge computing, which often suffer from poor memory locality or excessive memory footprint. To overcome these challenges, the authors propose a hardware-software co-design that integrates a tensor memory engine into the general-purpose CPU datapath. This engine enables runtime dynamic reconfiguration of memory layouts to significantly enhance cache locality, without requiring application code modifications, offloading computation to memory, or incurring memory overhead. By preserving the CPU’s role as the primary compute unit, the approach effectively improves overall system performance. Notably, this study presents the first practical implementation of runtime memory layout reconfiguration on commercial SoC/FPGA platforms, demonstrating both innovation and real-world applicability.

This work addresses the prohibitively high memory consumption of full-parameter fine-tuning, which hinders deployment on consumer-grade GPUs, by proposing ChunkFT—a novel framework that enables byte-streaming full-parameter fine-tuning without any model architecture modifications. ChunkFT introduces a dynamic activation working-set mechanism to stream parameter chunks during optimization, supporting gradient computation for arbitrary sub-tensors. It further incorporates memory-efficient optimizer state management and maintains compatibility with standard backpropagation, ensuring theoretical convergence while drastically reducing GPU memory requirements. Experiments demonstrate that ChunkFT fine-tunes Llama-3-8B on a single RTX 4090 with only 13.72 GB of VRAM and successfully scales to 70B models on two H800 GPUs, achieving downstream task performance that matches or even surpasses conventional full fine-tuning and outperforms existing parameter-efficient methods.

This work addresses the tension between logical data partitioning in production environments and efficient GPU utilization by proposing a streaming GPU encoding system. The system introduces a SuperBatch mechanism to uniformly process heterogeneous partitioned data, integrating a precise throughput prediction model, a streaming dual-threshold strategy bounded by memory safety margins, and an adaptability decision framework (φ/CV) to simultaneously achieve high throughput, bounded memory usage, low latency, and strong fault tolerance. By incorporating zero-copy Arrow serialization and an asynchronous I/O pipeline, the system attains a throughput of 26,413 samples per second on a 10-million-text dataset while consuming only 2.6 GB of memory—1/12.6 of the baseline—and reduces first-output latency by 68×, all while maintaining a 7% throughput advantage over the baseline.