real-time systems

This work addresses the challenge of achieving bounded, verifiable, and deterministic coordination in safety-critical real-time autonomous systems operating under uncertainty. It proposes a hardware-enforced semantic coordination architecture that, for the first time, directly maps a topic-based communication space Petri net (TB-CSPN) coordination mechanism onto the FPGA hardware layer. By leveraging hardware primitives to construct a native semantic coordination layer, the approach ensures deterministic execution of time synchronization, semantic gating, authorization constraints, and bounded coordination behaviors—without relying on software mediation. The design decouples low-level interaction management from high-level semantic reasoning, thereby preserving software adaptability while guaranteeing hardware-level reliability. This integration yields a highly dependable real-time system architecture with formally verifiable safety assurances, deterministic coordination, and bounded latency.

Existing heterogeneous accelerator designs primarily prioritize throughput or quality of service, falling short in meeting the stringent requirements of safety-critical real-time systems—namely, predictability, real-time awareness, and rigorous schedulability. This work proposes PHAROS, a novel framework that, for the first time, integrates modern real-time scheduling theory into heterogeneous accelerator design. PHAROS introduces a preemptive scheduling mechanism supporting both FIFO and EDF policies and formulates a soft real-time schedulability analysis model. Building upon this foundation, it develops a schedulability-driven design space exploration algorithm. Experimental results demonstrate that PHAROS significantly improves task set schedulability and real-time responsiveness across diverse applications, uncovering a substantially broader range of feasible configurations compared to throughput-oriented approaches.

Current 3GPP and O-RAN standards lack cross-device coordination abstractions for time-sensitive medical workflows, hindering their ability to meet the stringent requirements of emergency care scenarios. This work proposes the Collective Adaptive Intelligence Plane (CAIP), which enables workflow-level context binding, deadline-aware scheduling, semantic stream association, and data locality-based privacy preservation through lightweight coordination mechanisms compatible with existing RRC, QoS/SDAP, and O-RAN E2 interfaces—without introducing new protocol layers. CAIP represents the first integration of workflow coordination abstractions into the 6G healthcare networking standards framework, supports incremental deployment on 5G Advanced, and provides a standardized evolutionary path toward 6G. Its feasibility has been validated in an ICU collaboration scenario.

Centralized high-performance computing (HPC) platforms for software-defined vehicles require hybrid-criticality software architectures that simultaneously guarantee real-time performance, functional safety, and scalability—yet existing research lacks systematic empirical validation. Method: This paper pioneers the application of a rigorous systematic literature review (SLR) methodology to this domain, establishing a reproducible and transparent review protocol. We conduct functional-domain modeling, constraint extraction, and integration-pattern identification to synthesize key architectural practices. Contribution/Results: We propose a practice-oriented architectural guideline tailored for HPC platforms and design an implementable, microprocessor-based SoC-level hybrid-criticality software reference architecture. Our work bridges the methodological gap between theoretical frameworks and industrial deployment, providing empirically grounded foundations for standardizing automotive software development and offering industrially viable adaptation strategies.

In highly dynamic multimodal transportation environments, conventional centralized control architectures struggle to meet the stringent requirements of low latency, high reliability, and scalability in communication. This work proposes a hierarchical distributed architecture that integrates Software-Defined Networking (SDN) with Multi-access Edge Computing (MEC), combining regional coordination with edge autonomy to enable local failover and adaptive interface management, thereby eliminating dependence on a central node. Experimental results demonstrate that the control-plane communication and flow establishment latency between the designed edge SDN controllers and Pods are significantly lower than those of existing approaches, confirming the proposed architecture’s superior efficiency and practicality.

In multi-stakeholder platforms, software architecture decisions often implicitly entrench conflicting requirements without systematic support for mapping governance principles to technical design. This work proposes the first governance-architecture alignment framework, explicitly linking five core governance principles to the space of architectural decisions, thereby rendering implicit governance stances identifiable and contestable. The framework also exposes how default technical choices can obscure underlying value commitments. Feasibility is preliminarily demonstrated through a constructive case study of a pig-farming knowledge platform in Rwanda. Future work will employ pre- and post-intervention user judgment studies to evaluate the framework’s impact on actual governance outcomes.

Consumer-grade robots must concurrently execute safety-critical control, perception pipelines, and user applications on shared multicore platforms. However, conventional statically partitioned hypervisors struggle to simultaneously ensure strong isolation and support user-defined flexibility, further exacerbated by a knowledge gap between developers and end users regarding system-level constraints. This work proposes an integrated architecture combining secure I/O units, a cross-domain parameter synchronization service, and an IEC 61508-compliant safety communication layer. Implemented on an ARM Cortex-A55 platform, it achieves the first co-design of hardware-enforced isolation, encapsulated parameter management, and standardized safety communication. Empirical evaluation demonstrates an 84.5% reduction in cycle jitter and a decrease in 99th-percentile timing error from 69.0 μs to 7.8 μs, completely eliminating timing anomalies exceeding 50 μs, thereby effectively reconciling stringent safety requirements with user customization demands.

This study addresses the challenge of simultaneously achieving spatial abstraction, temporal predictability, and state continuity in ROS 2 middleware operating within dynamic, resource-constrained wireless environments. For the first time, it introduces a three-dimensional “space–time–state” analytical framework, integrating architectural analysis, formal modeling, and a comprehensive literature review to systematically investigate the underlying mechanisms and structural trade-offs of ROS 2 middleware—particularly DDS and Zenoh—in discovery protocols, data exchange, and state management. The work uncovers critical performance bottlenecks in existing approaches concerning modular deployment, real-time control, and disconnected operation recovery. These insights lay a theoretical foundation and offer concrete design guidelines for developing robust, scalable next-generation robotic middleware.

This study addresses the limitations of software-defined vehicles (SDVs) stemming from tight hardware-software coupling, which hinders modularity, interoperability, real-time performance, and over-the-air (OTA) update capabilities. The work presents the first systematic evaluation of hardware abstraction layer (HAL) mechanisms across automotive and non-automotive domains—including smartphones and industrial automation—and establishes a standardized assessment framework tailored to SDV requirements. Comparative analysis reveals that hypervisor-based HALs excel in security, OTA support, and hardware efficiency, whereas middleware-based HALs offer superior portability and modularity. Building on these insights, the paper proposes a hybrid HAL architecture that synergistically combines the strengths of both approaches, delivering a scalable, lifecycle-aware hardware abstraction solution for SDVs that ensures secure isolation while providing standardized interfaces.