design hardware abstraction layers

This study addresses the limitations of software-defined vehicles (SDVs) stemming from tight hardware-software coupling, which hinders modularity, interoperability, real-time performance, and over-the-air (OTA) update capabilities. The work presents the first systematic evaluation of hardware abstraction layer (HAL) mechanisms across automotive and non-automotive domains—including smartphones and industrial automation—and establishes a standardized assessment framework tailored to SDV requirements. Comparative analysis reveals that hypervisor-based HALs excel in security, OTA support, and hardware efficiency, whereas middleware-based HALs offer superior portability and modularity. Building on these insights, the paper proposes a hybrid HAL architecture that synergistically combines the strengths of both approaches, delivering a scalable, lifecycle-aware hardware abstraction solution for SDVs that ensures secure isolation while providing standardized interfaces.

Misuse of Hardware Abstraction Layer (HAL) interfaces in embedded systems frequently leads to runtime failures or even hardware damage; conventional software model checking suffers from unpredictable verification outcomes, hindering stable industrial adoption. Method: This paper proposes a continuous verification methodology tailored to HAL interface specifications, grounded in skeleton-based development with iterative functional extension and round-wise model checking. It introduces the first approach enabling cross-iteration reuse of abstract information without formal stepwise correspondence, thereby enhancing verification predictability and stability. The method integrates automated program abstraction inference with lightweight model checking. Results: Evaluated on real-world embedded applications, it successfully passes HAL specification verification across all development iterations and the final implementation, achieving 100% verification success rate—effectively overcoming the verification uncertainty bottleneck in industrial practice.

Identifying critical safety constraints from the vast number of Hardware Abstraction Layer (HAL) interfaces in embedded systems remains challenging, hindering effective fault prevention. Method: This paper proposes a fault-prevention-oriented requirement prioritization approach. Its core innovation is the formal definition of “indisputable relevance,” transforming hardware access constraint identification into a verifiable formal verification problem. The method models HAL interfaces, semantically analyzes real-world failure reports, and leverages model checkers (e.g., CBMC) to automatically generate mathematical proofs—thereby extracting and verifying constraints strongly correlated with system failures or hardware damage. Results: Evaluated on three industrial-grade failure cases involving the SPI bus spidev HAL, the approach successfully identified and formally verified critical requirements. Experimental results demonstrate its feasibility and effectiveness, establishing a novel, verifiable, and traceable paradigm for requirements engineering in high-reliability embedded systems.

To address the low efficiency and error-proneness of manual development and integration of software components in embedded systems, this paper proposes an Abstract Syntax Tree (AST)-driven Retrieval-Augmented Generation (RAG) method for fully automated, zero-intervention generation and formal verification of microcontroller Hardware Abstraction Layer (HAL) code. Focusing on the STM32F407 GPIO module, the approach integrates AST-based semantic analysis, RAG-enabled dynamic knowledge retrieval, static code verification, and HAL framework adaptation to ensure syntactic correctness, semantic consistency, and platform compatibility. Experimental evaluation demonstrates that the generated HAL code is functionally complete, directly compilable and flashable, and passes comprehensive functional testing on real hardware across all operational scenarios, achieving 98.7% accuracy. This work establishes the first end-to-end pipeline for automated HAL code generation coupled with formal verification in embedded systems.

This work addresses the inefficiencies and semantic inconsistencies arising from separately implementing driver and monitor programs in traditional hardware module testing. To overcome this, the authors propose a domain-specific language (DSL) tailored to hardware communication protocols, which enables the unified specification of both driver and monitor logic through an imperative syntax, thereby ensuring their semantic consistency for the first time. Building upon this DSL, they develop a prototype tool that leverages waveform parsing and transaction-level trace inference techniques to accurately reconstruct protocol-compliant transaction sequences from raw signal waveforms. Experimental results demonstrate that the approach significantly improves development efficiency, with further validation planned on real-world interconnect protocols such as Wishbone and AXI-Stream.

Formal methods face high adoption barriers in industrial embedded software due to prohibitive specification costs and low verification efficiency. Method: This paper introduces Temporal HAL-API Dependencies (THADs)—a lightweight, annotatable class of correctness properties that abstract temporal dependencies via HAL-API modeling. THADs are specified via low-overhead inline program annotations and automatically verified by a software model checker. Contribution/Results: To our knowledge, this is the first practical compromise bridging generic static analysis and full formal verification. Experiments demonstrate substantial reductions in specification effort, significantly improved verification automation, and support for scalable, cost-effective formal development. THADs exhibit strong applicability and deployment potential in real-world industrial embedded systems.

To address the challenges of co-modeling multi-source heterogeneous resources (e.g., hardware, software, networks, and microservices) and ensuring robustness in complex web applications, this paper proposes Chips—a domain-specific language (DSL) that integrates control-theoretic principles with general-purpose programming paradigms. Chips enables modular, function-oriented construction of discrete adaptive systems and introduces the first formally verifiable, component-based modeling approach that jointly ensures system-level adaptability and quality-of-service guarantees. Evaluated on the Adaptable TeaStore benchmark, Chips demonstrates substantial improvements in model composability, runtime dynamic adaptability, and fault tolerance. Moreover, it enhances both modeling efficiency and the rigor of reliability analysis.

To address the lack of integrated, reproducible, and pedagogically suitable gate-level netlist analysis tools in hardware reverse engineering, this paper introduces and open-sources NetSAT—the first unified, extensible, and education-friendly gate-level netlist analysis framework. Implemented in C++ and Python, NetSAT features an interactive Qt GUI, dual-language (C++/Python) APIs, and a modular plugin architecture. It innovatively integrates word-level abstraction modeling, graph-structural mining, cryptographic feature identification, and co-simulation capabilities to enable automated functional module decomposition and semantic understanding of netlists. NetSAT has been cited in over 23 peer-reviewed academic publications, adopted in university curricula and international conference tutorials, and garnered more than 680 GitHub stars and 86 forks. It is now widely recognized as a de facto standard tool for hardware security analysis in both industry and government agencies.

Current Trusted Execution Environment (TEE) solutions exhibit high heterogeneity and lack a unified abstraction layer, hindering the generality and development efficiency of confidential computing. Method: This paper systematically surveys the TEE technology landscape and proposes, for the first time, a design-oriented knowledge framework for TEE abstraction layers. Through multidimensional comparative analysis of mainstream architectures—including Intel SGX, ARM TrustZone, and AMD SEV—it identifies WebAssembly as the most capable cross-platform abstraction pathway. A comprehensive, full-stack classification framework for TEE abstraction layers is then constructed to precisely characterize capability boundaries and interoperability across implementations. Contribution/Results: The work delivers a practical abstraction modeling methodology and security interface design guidelines for heterogeneous TEE ecosystems, significantly enhancing the portability of confidential applications and improving development productivity.