dram pufs

This work addresses the vulnerability of delay-based physically unclonable functions (PUFs) to stealthy hardware Trojan insertion, which exploits process-induced timing uncertainties—a threat inadequately mitigated by existing security verification methods. For the first time, the study integrates PUF security and hardware Trojan risks into a unified circuit-level simulation framework to systematically evaluate multiple delay-based PUF architectures in terms of functional reliability, hardware overhead, and resistance to machine learning modeling, both before and after Trojan implantation. Experimental results demonstrate that dormant Trojans can preserve normal PUF behavior and modeling resilience, revealing critical blind spots in current PUF validation approaches that fail to detect such threats prior to Trojan activation.

This work proposes a physical unclonable function based on Simultaneous Multi-Row Activation of DRAM (SiMRA-PUF), which generates highly unique and reproducible device fingerprints without requiring any hardware modifications to commercial off-the-shelf (COTS) DDR4 chips. Experimental evaluation across 112 modern DDR4 devices demonstrates that, under activation configurations ranging from 2 to 32 rows, the intra-device Jaccard similarity ranges from 89.02% to 94.86%, while inter-device similarity remains low at 2.37%–3.98%. Notably, the 2-row activation configuration achieves a 5.75% improvement in evaluation speed over existing DRAM PUFs. This study presents the first practical DRAM-based PUF that simultaneously offers low latency, high reliability, and compatibility with unmodified commodity hardware, making it well-suited for real-world security applications.

This study systematically evaluates the reliability differences of embedded SRAM-based physically unclonable functions (PUFs) in two structurally similar microcontrollers across a temperature range of 10°C to 50°C. By executing identical SRAM PUF enrollment procedures and analyzing the randomness and stability of power-up states, the work presents the first quantitative comparison of SRAM PUF temperature sensitivity between otherwise comparable chips. Experimental results reveal that one SRAM implementation exhibits significantly superior PUF performance over the wide temperature range compared to the other, thereby demonstrating that underlying SRAM design critically influences PUF characteristics. These findings provide empirical evidence to guide early-stage chip selection for security-sensitive applications requiring robust PUF behavior under varying thermal conditions.

To address integrity and authenticity risks in FPGA-based embedded systems—where malicious binaries may bypass hardware authentication—this paper proposes a PUF-driven lightweight runtime binary binding and authentication mechanism. The method requires no hardware redesign or binary modification, supports bare-metal execution, and enables platform-agnostic deployment. It leverages the PicoBlaze soft-core processor on Xilinx FPGAs to generate PUF-based signatures and perform real-time integrity verification. Its key contribution is the first zero-dependency, modification-free, full-stack-compatible PUF-software co-authentication scheme. Hardware overhead is significantly lower than existing approaches, while achieving low verification latency and high throughput—fully optimized for resource-constrained bare-metal environments.

This work addresses three key limitations of conventional PUFs: limited challenge space, high hardware overhead, and incompatibility with asymmetric cryptography. To this end, we propose a novel PUF design based on pre-formed resistive random-access memory (ReRAM). Our method exploits the intrinsic resistance fluctuations of unformed ReRAM cells under low-voltage read operations, combined with a differential sensing circuit and a lightweight fingerprint extraction algorithm, to generate high-entropy responses. The key innovation lies in the first direct utilization of the analog-state randomness inherent in pre-formed ReRAM for PUF construction—eliminating the need for additional forming steps. This approach achieves a vastly expanded challenge space (up to 2⁶⁴), while ensuring high uniqueness (>99.7%), excellent stability (bit error rate <0.01%), and strong randomness (NIST statistical test suite pass rate >99%). The design has been fabricated and validated on a real ReRAM chip, offering an scalable, low-power, cryptographically primitive–enabled hardware security primitive for embedded systems.

This work addresses the high authentication error rates in SRAM physically unclonable functions (PUFs) deployed on resource-constrained industrial IoT devices, stemming from their inherent unreliability. To mitigate this issue, the authors propose a lightweight stabilization scheme that integrates Hamming code error correction (HC) with time-based majority voting (TMV), complemented by a threshold-tunable authentication mechanism. A key innovation lies in reframing the gap between reliability and security constraints as a design budget, which guides resource-aware parameter configuration to simultaneously ensure security and minimize overhead. Experimental results demonstrate that the proposed approach reduces the post-authentication bit error rate to below 1%, effectively establishing a PUF design space that balances error correction capability with resource efficiency.

This work proposes a lightweight software-hardware binding mechanism to protect sensitive tuning data—such as PID parameters—that constitute core intellectual property in embedded software from unauthorized extraction or reuse by cloned devices. The approach securely binds this sensitive data to device-unique SRAM-based Physical Unclonable Functions (PUFs) through Boolean logic operations, requiring no additional hardware. While unauthorized clones may execute the software, they suffer significant performance degradation due to the absence of the correct hardware fingerprint, and attackers face substantially increased difficulty in recovering the secret through dynamic analysis. Experimental evaluation on real-world microcontroller units (MCUs) demonstrates the effectiveness and practicality of the proposed scheme.

This study addresses the vulnerability of sensor data in industrial control systems to faults and supply chain attacks, exacerbated by the absence of an intrinsic trust mechanism at the measurement layer. To overcome this, the authors propose a process-aware, vendor-agnostic security architecture that embeds a Physical Unclonable Function (PUF) as a hardware root of trust directly within the sensor measurement layer. By integrating voltage-based fingerprinting with a time-based authentication mechanism, the framework enables real-time verification of sensor readings without requiring modifications to existing systems or compromising compatibility with standard industrial control architectures. Validation via a Simulink-based hardware-in-the-loop (HIL) platform demonstrates 99.97% authentication accuracy over 5.18 hours of operation and successful detection of all injected anomalies, including spike faults, hard overloads, and hardware trojans designed to induce unsafe system states.

This work addresses a critical reliability challenge in Processing-using-DRAM (PuD) systems, where high-density DRAMs are vulnerable to disturbances from inactive rows and concurrent column accesses, leading to computational errors. Through empirical evaluation on 96 real DDR4 chips, the study identifies and formally names this interference phenomenon “PuDGhost,” demonstrating that it can induce error rates as high as 10% from inactive rows and 48% from concurrent columns. To mitigate PuDGhost, the authors propose a cross-layer co-design combining hardware and layout optimizations, including Synchronized Multi-Row Activation (SiMRA), a column filtering strategy, and dedicated isolation rows. This integrated approach significantly enhances the robustness of PuD computation and lays a foundation for building reliable PuD systems.

This study addresses the lack of a unified and scalable authentication mechanism for heterogeneous IoT devices employing diverse physical unclonable functions (PUFs). To overcome this challenge, the authors propose a reference-data-free open-set PUF authentication framework that encodes raw responses from various PUF types—including strong, weak, and hybrid variants—into a common image representation. Coupled with an OpenGAN-based classifier, the framework enables one-shot authentication while effectively rejecting impostors. Notably, it is the first approach to support unified open-set authentication across heterogeneous PUFs, breaking the scalability barrier of prior methods limited to 3–5 devices and demonstrating efficient authentication of up to 45 distinct devices. Experimental results show 100% closed-set accuracy and near-zero open-set error rates across four noisy PUF datasets, with a Raspberry Pi prototype achieving single authentication in just 0.67 seconds—approximately 30× faster than existing open-set baselines.