nems puf design

This work proposes a novel hardware security paradigm based on nanoelectromechanical systems (NEMS) to address escalating threats in semiconductor manufacturing and advanced packaging, including hardware tampering, counterfeiting, and supply chain attacks. By harnessing the intrinsic mechanical unpredictability of NEMS and leveraging nanofabrication process variations as security features, the approach innovatively integrates physical unclonable functions (PUFs), shape-memory materials, resonant fingerprinting, and physically locked architectures. The resulting device-level security primitive offers strong resistance to reverse engineering and side-channel attacks while maintaining low power consumption. Designed for seamless integration into standard semiconductor fabrication processes, the solution demonstrates high robustness and scalability, showing significant protective efficacy for applications in defense, aerospace, critical infrastructure, and consumer electronics.

To address physical attacks and hardware cloning threats against IoT devices in third-party foundry environments, this paper proposes a novel Arbiter PUF architecture leveraging the Stanford memristor model. The design uniquely exploits the intrinsic stochasticity of filament evolution in memristors to enhance response reliability and resistance to modeling attacks. A co-modeling framework based on 45-nm CMOS technology is employed, integrating Monte Carlo simulations and Hamming distance analysis to rigorously evaluate uniqueness and stability under process variations, temperature fluctuations, and supply voltage deviations. Experimental results demonstrate that the memristor-based PUF achieves significantly higher reliability than conventional CMOS PUFs; while uniqueness shows room for further optimization, the architecture validates the efficacy of memristors in realizing robust hardware security primitives and highlights their practical potential for secure IoT authentication.

This work addresses the vulnerability of delay-based physically unclonable functions (PUFs) to stealthy hardware Trojan insertion, which exploits process-induced timing uncertainties—a threat inadequately mitigated by existing security verification methods. For the first time, the study integrates PUF security and hardware Trojan risks into a unified circuit-level simulation framework to systematically evaluate multiple delay-based PUF architectures in terms of functional reliability, hardware overhead, and resistance to machine learning modeling, both before and after Trojan implantation. Experimental results demonstrate that dormant Trojans can preserve normal PUF behavior and modeling resilience, revealing critical blind spots in current PUF validation approaches that fail to detect such threats prior to Trojan activation.

NVM-based PUFs suffer from endurance degradation and declining response stability due to cell wear under prolonged write operations, while remaining vulnerable to machine learning (ML) attacks. Method: This work establishes, for the first time, a quantitative model linking endurance degradation to PUF response quality—specifically uniqueness, randomness, and stability—and proposes a synergistic architecture combining write-load balancing scheduling with cell-stress suppression, integrated with an ML-resistant response perturbation mechanism. Contribution/Results: The proposed approach achieves a 62× improvement in endurance while maintaining high uniqueness (>99.7%), low bias (<0.01%), and robust ML resistance—yielding <0.5% misidentification rates against state-of-the-art LSTM and MLP attackers. This work pioneers a co-design paradigm for NVM PUFs that jointly optimizes endurance and security.

This work exposes critical security vulnerabilities in practical deployments of paper-based Physical Unclonable Function (PUF) anti-counterfeiting authentication systems. Addressing the lack of systematic security modeling and susceptibility to cross-domain attacks in existing approaches, we propose the first end-to-end formal security model for paper PUFs. We identify and implement two novel attack paradigms: physical-layer denial-of-service attacks and digital-layer image forgery attacks, and establish a phased security analysis framework. Experimental evaluation demonstrates significant authentication bypass risks across mainstream paper PUF schemes. Our study not only uncovers a previously underexplored physical–digital co-attack vector but also provides a reusable, methodology-driven security assessment framework. The results lay both theoretical foundations and practical guidelines for designing robust, attack-resilient PUF systems.

This study addresses the critical need for hardware-rooted trust mechanisms in resource-constrained and physically exposed AIoT systems that effectively balance security and practicality. It presents the first systematic survey and comparative analysis of Trusted Platform Modules (TPMs), silicon- and FPGA-based Physically Unclonable Functions (PUFs), container-aware hybrid roots of trust, and purely software-based approaches, evaluating their trade-offs across key dimensions including security, scalability, cost, and deployment complexity in AIoT contexts. The findings demonstrate that PUFs and hybrid architectures offer significant advantages in resisting physical attacks and device cloning, thereby providing essential design guidance for building trustworthy edge AI platforms.

本文针对物联网系统中的人、设备和功能的信任问题，通过整合生物识别、物理不可克隆函数及硬件混淆方法来建立跨层信任机制。

This study addresses the lack of a unified and scalable authentication mechanism for heterogeneous IoT devices employing diverse physical unclonable functions (PUFs). To overcome this challenge, the authors propose a reference-data-free open-set PUF authentication framework that encodes raw responses from various PUF types—including strong, weak, and hybrid variants—into a common image representation. Coupled with an OpenGAN-based classifier, the framework enables one-shot authentication while effectively rejecting impostors. Notably, it is the first approach to support unified open-set authentication across heterogeneous PUFs, breaking the scalability barrier of prior methods limited to 3–5 devices and demonstrating efficient authentication of up to 45 distinct devices. Experimental results show 100% closed-set accuracy and near-zero open-set error rates across four noisy PUF datasets, with a Raspberry Pi prototype achieving single authentication in just 0.67 seconds—approximately 30× faster than existing open-set baselines.

This work addresses the vulnerability of physical unclonable functions (PUFs) in Internet of Things (IoT) devices to machine learning (ML)-based modeling attacks by proposing a lightweight, dynamically reconfigurable RC-PUF architecture with minimal structural complexity and resource overhead. The design enhances nonlinearity and randomness through 32-bit challenge-response pairs and rigorously evaluates resistance to ML/DL attacks using multiple advanced models—including artificial neural networks (ANN), gradient-boosted neural networks (GBNN), decision trees (DT), random forests (RF), and XGBoost—trained on systematically partitioned datasets. Experimental results demonstrate that all attack models achieve prediction accuracies on the test set close to random guessing (50%–53%), thereby significantly improving robustness against ML/DL-based modeling attacks and confirming the effectiveness and practicality of the proposed scheme for hardware security applications.

This work addresses the high authentication error rates in SRAM physically unclonable functions (PUFs) deployed on resource-constrained industrial IoT devices, stemming from their inherent unreliability. To mitigate this issue, the authors propose a lightweight stabilization scheme that integrates Hamming code error correction (HC) with time-based majority voting (TMV), complemented by a threshold-tunable authentication mechanism. A key innovation lies in reframing the gap between reliability and security constraints as a design budget, which guides resource-aware parameter configuration to simultaneously ensure security and minimize overhead. Experimental results demonstrate that the proposed approach reduces the post-authentication bit error rate to below 1%, effectively establishing a PUF design space that balances error correction capability with resource efficiency.