encode problems as ising/spin models

Combinatorial optimization problems face scalability bottlenecks on Ising machines due to physical limitations in qubit count and connectivity. To address this, we propose a heterogeneous Ising multi-processor architecture that integrates multiple physical spin cores—such as superconducting qubits and electronic oscillators—of varying scales and topologies on a single chip, enabling problem-driven dynamic core matching and collaborative scheduling. We introduce the first hardware-constrained quantitative evaluation framework for heterogeneous Ising architectures, rigorously validating its advantages in time-to-solution, energy efficiency, and solution quality under identical hardware budgets and spin technologies. Experimental results across a standard combinatorial optimization benchmark suite demonstrate that our approach achieves, on average, a 2.3× speedup, 37% lower energy consumption, and a 12.5% improvement in solution quality compared to homogeneous counterparts.

Conventional QUBO modeling for polymorphic Ising problems causes exponential solution-space expansion and degraded solution quality. Method: We propose a generalized Boolean logic modeling framework that directly encodes polymorphic spin interactions—bypassing QUBO conversion—and achieve, for the first time, deep synergy between parallel annealing and probabilistic Ising solvers. We further design a dedicated 1024-neuron fully connected accelerator optimized for energy efficiency, silicon area, and solution quality. Results: On graph coloring benchmarks, our approach matches state-of-the-art heuristic and machine learning methods in accuracy, reduces error rate by 50% versus conventional Ising formulations, achieves a 10⁴× speedup, and cuts physical neuron requirements by 1.5–4×—surpassing all existing approaches across all key metrics.

Existing Ising machines solve combinatorial optimization problems with linear constraints (e.g., multidimensional/quadradic knapsack problems) by imposing manually tuned large penalty coefficients, which distort the energy landscape, impede convergence, and degrade solution quality. This work proposes an adaptive Ising machine framework that—uniquely—integrates Lagrangian relaxation with iterative energy shaping to dynamically reshape the energy landscape during search, eliminating the need for predefined hard-constraint penalty terms. Implemented via p-bit–based software simulation, the paradigm balances constraint satisfaction and objective optimization in real time through Lagrangian dual updates. Evaluated on a 300-variable quadratic knapsack problem, our approach achieves superior solution quality compared to Fujitsu’s Digital Annealer and improves sampling efficiency by 7,500×, significantly enhancing robustness and scalability for constrained optimization.

Existing Ising solvers predominantly rely on simulated annealing, lacking theoretical convergence guarantees and exhibiting sensitivity to cooling schedules. This paper proposes a novel continuous optimization framework: binary spins are relaxed to continuous variables; a certifiably coercive attraction potential function is introduced to drive solutions toward binary values; and the energy minimization problem is formulated as a difference-of-convex (DC) program. The method enjoys global convergence guarantees, eliminates the need for annealing schedules, and requires only one matrix-vector multiplication per iteration—ensuring high computational efficiency. Implemented on GPU platforms—from edge devices to supercomputing clusters—it scales to Ising systems with up to 100 million spins and significantly outperforms state-of-the-art solvers on problems ranging from 10³ to 10⁶ spins. The core innovation lies in the principled integration of continuous relaxation, structured attraction potentials, and DC programming—enabling, for the first time, provably convergent, highly scalable, and low-overhead ground-state computation for large-scale Ising models.

This work addresses the challenge of automatically mapping and efficiently solving combinatorial optimization problems on probabilistic computing architectures. It proposes an Ising-model-based automated mapping approach that translates optimization problems into hardware-compatible formulations by constructing corresponding Hamiltonians and configuring the number of p-bits. A key innovation is the introduction of an adaptive algorithm selection mechanism that dynamically switches among Gibbs sampling, simulated annealing, simulated quantum annealing, and cluster updates to significantly enhance convergence speed and robustness. Validated through MTJ-based hardware modeling on standard benchmark instances, the proposed framework demonstrates superior performance over fixed-strategy approaches, offering a scalable and systematic co-design and evaluation paradigm for probabilistic computing systems.

This study addresses the optimization and sampling efficiency bottlenecks arising from the absence of hardware-software co-design in Ising machines by proposing a top-down co-design framework. Methodologically, it systematically reviews cross-platform probabilistic algorithms—including simulated annealing, parallel tempering, cluster mean-field, and variational samplers—while deeply integrating the classical QAOA-analogous PAOA algorithm with large language model inference techniques and probabilistic hardware. This integration reveals a bidirectional enhancement mechanism between generative AI and Ising machines. The primary contribution lies in establishing a co-design theoretical framework that accelerates the capability evolution and widespread adoption of next-generation Ising machines, significantly expanding the scale of tractable problems.

This work addresses the scalability limitations of large-scale Ising problem solvers, which are hindered by the physical constraints of analog solvers and the high latency introduced by conventional CPU-based decomposition. The authors propose a tightly coupled heterogeneous architecture that, for the first time, offloads the Ising problem decomposition task onto an FPGA, operating in concert with a custom 28nm analog Ising solver. Leveraging the FPGA’s reconfigurable parallel processing capabilities, the system substantially reduces communication latency and achieves efficient hardware-software co-design. Compared to an optimized CPU-based software baseline, the proposed system demonstrates nearly a 2× speedup and improves energy efficiency by over two orders of magnitude.

This work addresses the combinatorial optimization challenge of test case selection and minimization in software testing by proposing IsingTester, a novel framework that introduces Coherent Ising Machines (CIMs) to the domain of test optimization for the first time. The approach formulates the problem as an Ising model, encoding optimization objectives into spin configurations, and integrates multiple solvers—including CIM simulation and exhaustive search—into an end-to-end automated optimization pipeline. To facilitate systematic evaluation and comparison of diverse solution strategies, the authors also release IsingBench, a benchmark platform featuring extensible modeling interfaces and a reproducible experimental environment.

This work addresses the high sensitivity of measurement-feedback-based Ising machines to hyperparameters under discrete-time operation, which significantly narrows their effective tuning range compared to ideal continuous-time models and limits their optimization performance. The study systematically investigates the discrepancies between discrete-time implementation and continuous dynamics, uncovering the root causes of this hyperparameter sensitivity. Building on this analysis, the authors propose the first targeted mitigation strategy, combining discrete-time modeling, sensitivity analysis, and experimental validation. The proposed approach substantially broadens the effective operating regime, reduces reliance on precise hyperparameter settings, and thereby enhances the robustness, stability, and practical utility of hardware Ising machines for solving combinatorial optimization problems.

This work proposes the Bounce-Bind Ising Machine (BBIM) to address the inherent trade-off between solution speed and hardware resource constraints in Ising machines. BBIM introduces a single tunable parameter that dynamically switches between two spin dynamics modes—Bounce and Bind—without altering the energy landscape or incurring additional hardware overhead. The Bounce mode accelerates escape from local minima, while the Bind mode promotes rapid convergence. Inspired by an enhanced physical analogy based on a tennis-ball/lead-ball system, BBIM achieves up to 6.15× and 27.3× speedups on dense MAX-CUT instances (n=200) and sparse 3-Regular 3-XORSAT problems (n=160), respectively, significantly improving solution efficiency while maintaining high solution quality.