hdl implementation

Large language models (LLMs) often introduce functional errors in hardware description language (HDL) generation due to hallucination. This paper proposes CorrectHDL, the first LLM-based intelligent agent framework that leverages high-level synthesis (HLS) output as a *dynamic functional reference*—not a static target—to guide HDL generation. It integrates retrieval-augmented generation (RAG)-enhanced prompting, functional simulation-based verification, and iterative correction to jointly optimize functional correctness and hardware efficiency. Evaluated on benchmark circuits, CorrectHDL achieves 100% functional correctness while generating implementations with significantly smaller area and lower power consumption than conventional HLS tools—and approaching hand-designed RTL quality. The core innovation lies in transforming HLS results from a fixed specification into an adaptive, simulation-validated correction baseline, thereby enabling tight integration of generative design with formal verification. This validates the efficacy of a closed-loop “generate–verify–correct” paradigm for trustworthy HDL synthesis.

Large language models (LLMs) frequently generate Verilog code with hallucinations and high functional error rates. Method: This paper proposes a paradigm-block-driven, two-stage, multi-round generation framework. First, circuits are classified by type to retrieve human-expert-designed paradigm blocks—comprising information extraction, human-like design workflows, and EDA tool integration. Then, a closed-loop iterative process (“generate → simulate → feedback → correct”) refines the code within a bounded number of rounds. Contributions/Results: (1) It introduces the first LLM instruction framework guided by hardware design paradigm blocks; (2) it establishes a verifiable two-stage generation-and-verification mechanism. Experiments demonstrate a significant improvement in testbench pass rate, effectively mitigating semantic distortion and structural hallucination in LLM-generated HDL code.

This work addresses the limited adaptability of AI models to hardware design automation and security verification. We systematically survey attention-based mechanisms—including large language models (LLMs) and graph attention networks (GATs)—applied to RTL generation, vulnerability detection, and chip floorplanning. For the first time, we comprehensively analyze 30 representative methods and propose the LLM-HDL co-design paradigm: a cross-disciplinary framework integrating IP reuse and formal security verification. Leveraging HDL-specific datasets and RTL-level automated code generation, we realize an end-to-end closed-loop design flow. Our study identifies critical bottlenecks—including model interpretability, hardware-semantic alignment, and industrial deployment feasibility—and establishes a scalable, LLM-driven hardware design framework with a concrete roadmap for security enhancement. The framework bridges academic research and industrial practice, enabling rigorous, automated, and trustworthy hardware development.

Manual pragma configuration in high-level synthesis (HLS) suffers from low efficiency and an exponentially large search space. Method: This paper proposes the first nonlinear programming (NLP)-based automated pragma insertion framework, jointly optimizing loop-level pragmas—including pipelining, function unit replication, and data caching. It innovatively models discrete pragma configurations as continuous, differentiable variables and constructs analytical performance/resource models with theoretical lower-bound guarantees, solved globally via NLP. Integrated with pragma semantic analysis and the Merlin compiler, and augmented by design-space pruning, the framework explores billion-scale configurations within seconds to minutes. Contribution/Results: Experimental evaluation shows kernel performance approaching hand-tuned implementations, resource estimation error <8%, and latency lower-bound error ≤12%.

This work investigates the potential of large language models (LLMs) to enable natural-language-driven hardware logic design, aiming to improve design efficiency and programmability for hardware engineers. Method: We propose the first zero-code, four-stage LLM-driven framework that automates Verilog RTL design generation, correction, optimization, and multi-objective design-space search—entirely from natural-language specifications. Eschewing fine-tuning, our approach innovatively integrates prompt engineering, structured output control, Verilog syntax validation, and constraint-aware design-space search to establish a closed-loop hardware synthesis paradigm. Contribution/Results: Experiments across multiple benchmarks demonstrate significant improvements over both base LLMs and prior methods. Our framework is the first to generate functionally correct, complete, and area- and delay-optimizable RTL designs without any manual coding—thereby substantially expanding the feasibility frontier of AI-driven hardware design.

This work addresses the challenge that large language models (LLMs) often introduce semantic or logical errors when generating hardware RTL code, failing to meet the stringent reliability requirements of chip design. To overcome this limitation, the paper proposes a novel hardware generation framework that integrates LLMs with formal methods, uniquely combining LLM-driven iterative refinement with formal verification. The approach leverages predefined transformation rules to guide the LLM in progressively refining high-level specifications into RTL code that is formally verifiable for correctness. This integration enhances both the interpretability and reliability of the code generation process. Experimental results demonstrate that the method is not only effective but also efficient in producing correct RTL implementations, thereby offering a promising pathway toward trustworthy LLM-assisted hardware design.

This work addresses the limitations of existing high-level synthesis (HLS) tools in balancing sequential semantics with fine-grained control over pipeline design, which hinders optimization of power, performance, and area (PPA). The paper proposes a novel HLS approach based on visibility control that preserves a sequential programming model while enabling precise manipulation of pipeline structures and hazard-handling mechanisms through a unified visibility abstraction. This framework encompasses strategies such as stall insertion, bypassing, speculative execution, delayed commit, and register renaming. Experimental results on a RISC-V core, histogram computation, and an AES accelerator demonstrate that the generated pipelines significantly outperform those from state-of-the-art sequential-semantics-preserving HLS tools, achieving PPA metrics close to hand-optimized RTL implementations and enabling efficient design space exploration.

This work addresses the lack of synthesizable and formally verified IEEE-754 floating-point support in hardware description languages generated by current large models. It presents the first unified framework that simultaneously produces synthesizable SystemVerilog RTL, an SMT-LIB formal model, and a Lean 4 proof artifact from a single source, ensuring semantic consistency among all three through structural binding and machine-checked equivalence, thereby preventing semantic drift. Leveraging a bit-vector intermediate representation, the approach combines Yosys-to-SMT miter verification, SMT floating-point theories, and correctly rounded specifications over dyadic domains to formally verify 24 floating-point operators: non-multiplicative operators are exhaustively proven equivalent to SMT theory, while FP32 multiplication and fused multiply-add (FMA) are formally shown to be correctly rounded in Lean. An optimized 98-bit FMA pipeline achieves 268 MHz in Nangate45 and is proven bit-accurate against an exact reference model in Lean.

This work addresses the high failure rate of natural language–generated hardware descriptions during synthesis or tape-out, often caused by bit-width mismatches, combinational loops, or incomplete logic. It presents the first integration of dependent types and formal proof into a closed-loop hardware generation pipeline, leveraging Lean 4 to construct a verifiable hardware description language that guides large language models to produce type-safe and provably correct circuit code. By exposing design flaws at compile time, the approach achieves a backend implementation success rate of 95–100%, matches hand-written Verilog in simulation pass rates across three major benchmarks, automatically completes functional equivalence verification, and yields up to 35% area reduction and 30% power savings.

This work addresses the inefficiencies and semantic inconsistencies arising from separately implementing driver and monitor programs in traditional hardware module testing. To overcome this, the authors propose a domain-specific language (DSL) tailored to hardware communication protocols, which enables the unified specification of both driver and monitor logic through an imperative syntax, thereby ensuring their semantic consistency for the first time. Building upon this DSL, they develop a prototype tool that leverages waveform parsing and transaction-level trace inference techniques to accurately reconstruct protocol-compliant transaction sequences from raw signal waveforms. Experimental results demonstrate that the approach significantly improves development efficiency, with further validation planned on real-world interconnect protocols such as Wishbone and AXI-Stream.