noise-aware circuit synthesis

This paper presents a systematic survey of quantum circuit optimization, addressing the dual challenges of accelerating execution and mitigating noise-induced errors on Noisy Intermediate-Scale Quantum (NISQ) hardware—while preserving functional correctness. Methodologically, it unifies hardware-agnostic techniques (e.g., graph rewriting, algorithmic optimization) with hardware-aware approaches (e.g., instruction scheduling, NISQ-adaptive compilation), integrating heuristic search, reinforcement learning, supervised learning, and hybrid quantum-classical frameworks into a multidimensional evaluation framework. Key contributions include: (i) rigorous characterization of performance limits and robustness deficiencies across optimization paradigms; (ii) identification of three critical bottlenecks—deep compression, noise-aware optimization, and automated compiler design; and (iii) proposal of novel research directions in scalability, cross-platform generalization, and compilation robustness. The work provides both theoretical foundations and practical guidelines for advancing the quantum software stack.

This work addresses the challenges of high redundancy, noise sensitivity, and hardware mapping difficulties in quantum LDPC encoder circuits, which hinder efficient encoded state preparation in fault-tolerant quantum computing. The authors reformulate encoder construction as a reversible linear circuit resynthesis problem and introduce a bidirectional Hamming descent optimization method. By integrating CNOT block resynthesis, hardware-aware routing, and noise-aware scheduling strategies, the proposed approach significantly reduces circuit size and depth while respecting hardware constraints. Experimental results demonstrate an average 53.8% reduction in gate count across various CSS-LDPC codes—reaching up to 68% for Bivariate Bicycle codes—with post-routing two-qubit circuit depth reduced by as much as 71%. Furthermore, encoded state preparation failure rates decrease by up to 13.7%, yielding substantially improved fidelity.

This work addresses the gap between idealized noise-free models and real-world noisy quantum hardware in quantum program verification. It introduces, for the first time, a noise-aware quantum Hoare logic that integrates hardware-specific error models—such as those provided by IBM Qiskit—to define a realistic noisy semantics. The study further demonstrates the critical role of classical probabilistic branching in achieving optimality in quantum programs. Building on this foundation, the authors develop a bounded verification algorithm and an automated synthesis method capable of generating optimal quantum subroutines tailored to specific noise environments, including tasks like parity computation, state preparation, and state discrimination. The efficacy of the proposed approach is validated against actual hardware specifications.

Current quantum hardware exhibits highly spatially non-uniform noise, yet existing circuit cutting methods do not systematically account for such heterogeneous noise profiles, leading to exponentially growing sampling overhead. This work proposes a hardware noise-aware circuit cutting framework that explicitly incorporates spatial noise non-uniformity into the cutting strategy for the first time. By unifying gate and wire cutting within a single modeling framework and leveraging real-device noise maps to optimize subcircuit allocation and execution constraints, the method achieves exponential overhead reduction while maintaining low-noise alignment. Notably, it requires only minor relaxation of device constraints to avoid high-noise regions. Experiments demonstrate an average 5–54× reduction in required circuit executions on 20-qubit circuits and, for the first time, enable feasible cutting of 50-qubit circuits and application-level benchmarks, substantially outperforming conventional strategies.

This work addresses the joint compilation problem of qubit mapping and SWAP routing for surface-code-based fault-tolerant quantum computers. Recognizing that conventional decoupled optimization leads to suboptimal solutions, we propose a unified discrete optimization framework grounded in the operation dependency graph: both qubit mapping and SWAP insertion are jointly modeled as a coupling-constrained integer program. We further design a dependency-aware simulated annealing algorithm to achieve cooperative near-optimal compilation. Crucially, our approach is the first to explicitly incorporate fine-grained, operation-level data dependencies into the compilation optimization model, thereby significantly improving compilation quality and hardware adaptability. Evaluated on realistic quantum workloads—including QAOA and Shor’s algorithm subcircuits—our method reduces logical gate overhead by 32% on average and improves circuit fidelity by 27% compared to state-of-the-art compilers, while maintaining scalability.

Quantum circuit compilation faces challenges in jointly optimizing synthesis and routing under stringent hardware constraints, while conventional approaches—such as SAT solvers—are computationally prohibitive. Method: This work pioneers the systematic integration of deep reinforcement learning (specifically PPO and DQN) into end-to-end quantum compilation, incorporating circuit representation learning, topology-aware action space design, and native gate set adaptation. Contribution/Results: The method achieves joint synthesis and routing optimization for circuits up to 65/133 qubits, supporting synthesis on Linear/Clifford/Permutation benchmarks with capacities of 9/11/65 qubits, respectively. It reduces two-qubit gate depth and count significantly compared to SABRE and accelerates compilation by several orders of magnitude over SAT-based methods. By breaking the real-time versus optimality trade-off in hardware-aware compilation, this approach establishes a scalable, efficient compilation paradigm tailored for large-scale noisy intermediate-scale quantum (NISQ) devices.

Existing quantum compilers explore only a limited optimization pass search space and rely solely on static circuit features, making it difficult to accurately predict optimization outcomes. This work proposes QuTuner, a novel framework that, for the first time, integrates static circuit structural features with dynamic optimization-response embeddings to construct an optimization-aware pass representation. QuTuner employs an offline machine learning model to retrieve and rank candidate optimization sequences, augmented by lightweight online fine-tuning to enable adaptive, multi-objective tuning across different compilers. Experimental results on Qiskit and PyTKET demonstrate that QuTuner reduces optimization metrics by 84.85% and 18.68%, respectively, while cutting tuning time by 73.59% and 64.49%, substantially improving both tuning efficiency and effectiveness.

This work proposes a supervised learning–based auto-tuning approach to overcome the limitations of fixed-configuration optimization in traditional quantum circuit transpilation, which often fails to achieve optimal two-qubit gate reduction across diverse circuits. By integrating circuit feature modeling with machine learning, the method dynamically selects the best combination of optimization passes for the Qiskit transpiler. Trained on the MQT Bench benchmark suite, the predictive model transcends the constraints of predefined optimization levels. Experimental results demonstrate that, compared to Qiskit’s default settings, the proposed approach reduces two-qubit gate counts by an additional 19.1%–32.4% on average, with some circuits achieving up to a 95.8% reduction, thereby substantially enhancing transpilation efficiency.

This work addresses the limitations of existing high-level synthesis (HLS) tools in balancing sequential semantics with fine-grained control over pipeline design, which hinders optimization of power, performance, and area (PPA). The paper proposes a novel HLS approach based on visibility control that preserves a sequential programming model while enabling precise manipulation of pipeline structures and hazard-handling mechanisms through a unified visibility abstraction. This framework encompasses strategies such as stall insertion, bypassing, speculative execution, delayed commit, and register renaming. Experimental results on a RISC-V core, histogram computation, and an AES accelerator demonstrate that the generated pipelines significantly outperform those from state-of-the-art sequential-semantics-preserving HLS tools, achieving PPA metrics close to hand-optimized RTL implementations and enabling efficient design space exploration.

Existing quantum compiler benchmarks provide only aggregate fidelity metrics, making it difficult to pinpoint the sources of fidelity loss across different stages of the compilation pipeline. This work proposes the HBR decomposition framework, which partitions compilation into three distinct phases: high-level structure decomposition (H), basis gate translation (B), and routing (R), thereby enabling, for the first time, stage-wise fidelity attribution. Leveraging this model, the study evaluates eight quantum algorithms across varying optimization levels on Qiskit, PennyLane, and TKET, using both noise-aware simulations and real-device experiments on IBM Heron and IonQ Forte hardware topologies. The results accurately predict the relative performance ranking of the SDKs, reveal that the dominant performance bottleneck shifts with algorithm class and optimization level, and uncover phase-specific limitations invisible to conventional holistic benchmarks.