hardware-aware qubit mapping

This paper presents a systematic survey of quantum circuit optimization, addressing the dual challenges of accelerating execution and mitigating noise-induced errors on Noisy Intermediate-Scale Quantum (NISQ) hardware—while preserving functional correctness. Methodologically, it unifies hardware-agnostic techniques (e.g., graph rewriting, algorithmic optimization) with hardware-aware approaches (e.g., instruction scheduling, NISQ-adaptive compilation), integrating heuristic search, reinforcement learning, supervised learning, and hybrid quantum-classical frameworks into a multidimensional evaluation framework. Key contributions include: (i) rigorous characterization of performance limits and robustness deficiencies across optimization paradigms; (ii) identification of three critical bottlenecks—deep compression, noise-aware optimization, and automated compiler design; and (iii) proposal of novel research directions in scalability, cross-platform generalization, and compilation robustness. The work provides both theoretical foundations and practical guidelines for advancing the quantum software stack.

Quantum hardware suffers from sparse connectivity among physical qubits, necessitating SWAP gate insertion to map logical qubits onto the physical architecture—yet this increases gate count and circuit depth, severely degrading fidelity. To address this, we propose TANGO: a novel quantum circuit mapping algorithm featuring a bidirectional (forward-backward) look-ahead SWAP selection strategy. TANGO integrates layer-weighted initial qubit placement, a two-stage heuristic routing procedure, and joint gate merging and rescheduling optimizations—all while strictly respecting hardware connectivity constraints—to simultaneously minimize total gate count and circuit depth. Extensive evaluations on standard benchmark circuits and real quantum devices demonstrate that TANGO achieves average reductions of 18.7% in gate count and 15.2% in circuit depth over state-of-the-art methods, establishing new performance benchmarks in quantum compilation.

To address the problem of excessive SWAP gate insertion—necessitated by limited hardware connectivity in quantum devices—which increases circuit depth and error rates during logical-to-physical qubit mapping, this paper proposes HAIL, an efficient iterative mapping algorithm. Methodologically, HAIL introduces three key innovations: (1) a layer-weighted subgraph isomorphism initialization to enhance initial mapping quality; (2) a bidirectional iterative refinement framework that jointly optimizes qubit mapping and SWAP insertion sequences; and (3) a search-space compression strategy tailored for sparse architectures, complemented by a post-processing heuristic search. Evaluated on IBM Q20 (B23 benchmark), HAIL reduces extraneous SWAP gates by 20.62% over state-of-the-art methods. On Google Sycamore, it simultaneously lowers SWAP overhead and runtime, significantly improving mapping efficiency and circuit executability.

This work addresses the degradation of logical symmetry in symmetric quantum circuits when compiled on constrained hardware, where uneven routing overhead induced by SWAP operations disrupts inherent symmetries. The authors demonstrate that this imbalance stems not from hardware limitations but from conventional compiler mapping strategies. To mitigate this issue, they propose a symmetry-aware qubit allocation method that enforces balanced routing. Evaluated on a 57-qubit heavy-hex architecture through exhaustive search, symmetry-preserving modeling, and error simulation, the approach achieves zero additional circuit depth for feasible patches while reducing symmetry-breaking by 92.7%. Experimental results further confirm its substantial superiority over general-purpose compilation optimizations in preserving circuit symmetry.

This work addresses the critical bottleneck in compiling for trapped-ion quantum charge-coupled device (TI-QCCD) architectures, where qubit mapping and routing are constrained by physical limitations such as ion transport, trap capacity, and congestion. The authors propose a compilation framework based on a positional graph abstraction that uniformly models executable zones, movement paths, and routing constraints, integrating an enhanced SABRE-inspired heuristic search. Their approach innovatively introduces a relative movement scoring scheme and a memoized congestion-resolution mechanism, which substantially reduces redundant computations without altering scheduling decisions. This advancement significantly improves the scalability of SABRE-like algorithms on TI-QCCD platforms, offering an efficient and practical solution for qubit mapping and routing on heterogeneous quantum hardware.

This work addresses the limitations of silicon spin qubit platforms in quantum compilation, which are constrained by hardware-specific restrictions and static fabrication defects, and critically lack support for logical error correction in existing approaches. To bridge this gap, the study introduces the first integration of high-level logical circuit routing with a two-dimensional surface code error correction scheme. It proposes two adaptive routing algorithms—the shortest-path method and the rotation-based method—augmented with defect-aware initial mapping and layout optimization strategies. The shortest-path approach excels in low-defect, sparse scenarios, while the rotation-based method demonstrates superior performance under high defect densities. This research establishes a foundational framework for error-correction-aware compilation on silicon spin qubit architectures, with implementations publicly released in the MQT toolkit.

This work addresses the challenge of compiling for modular multi-quantum processor architectures by jointly optimizing local qubit connectivity and inter-QPU communication to mitigate communication congestion, port overloading, and imbalanced boundary qubit allocation. The authors propose QuPort, a compilation framework that explicitly models QPU communication port constraints and link congestion at the compiler level for the first time. QuPort introduces a three-layer graph model—comprising a logical interaction graph, a physical coupling graph, and a QPU interconnect graph—and devises a TPCCAP partitioning method that simultaneously optimizes cut-edge distance, port overflow, and link congestion. Through an integrated pipeline featuring port-aware placement, remote gate extraction, and topology-aware scheduling, QuPort significantly reduces inter-QPU communication overhead, balances port utilization, and enhances compilation efficiency without relying on hardware-specific protocols.

This work addresses the high communication overhead in distributed quantum computing arising from inter-node operations such as teleportation of quantum states and gates. To mitigate this, the authors propose a time-aware beam search heuristic that incrementally constructs low-communication qubit allocation sequences across discrete time steps, enabling efficient circuit partitioning. By integrating dynamic timing information with network topology, the method overcomes the limitations of conventional static graph partitioning and computationally expensive metaheuristic approaches. Experimental results demonstrate that the proposed algorithm consistently achieves substantial reductions in communication cost across diverse circuit sizes, depths, and network topologies, while maintaining time and space complexities of only quadratic in the number of qubits and linear in circuit depth, respectively.

This work addresses the NP-hard problem of dynamic qubit routing in quantum compilation by formulating it for the first time as a dynamic Quadratic Assignment Problem (QAP), where the logical gate interactions define the flow matrix and the hardware topology defines the distance matrix, yielding a unified optimization objective. The authors propose a Solution-aware Transformer policy network that explicitly captures interactions between the flow and distance matrices, augmented with a look-ahead mechanism naturally aligned with the QAP structure, enabling global routing decisions through reinforcement learning. Evaluated on three benchmarks—MQTBench, AgentQ, and QUEKO—the approach reduces CNOT gate counts by 15.7%, 30.4%, and 12.1%, respectively, significantly outperforming existing industrial compilers.