shuttling-aware compilation

Dynamic qubit routing—relocating ions involved in gate operations to the same trap segment via ion transport—is a critical challenge in segmented ion-trap quantum computers. Method: This work introduces the first layout-agnostic, large language model (LLM)-driven compilation paradigm. Unlike conventional topology-specific heuristics, it leverages pre-trained LLMs (e.g., LLaMA) and employs instruction tuning to jointly encode quantum circuits and arbitrary one-dimensional trap topologies (linear, ring, branched) into structured prompts, directly generating optimal transport sequences. Contribution/Results: Experiments demonstrate substantial improvements in compilation flexibility and scalability across diverse trap architectures. The approach establishes, for the first time, a unified, general-purpose, and transferable transport compilation infrastructure that operates consistently across topologies—eliminating the need for architecture-specific re-design and enabling seamless adaptation to novel trap layouts.

Quantum circuit compilation for QCCD-based trapped-ion quantum computers faces severe hardware constraints and low compilation efficiency. Method: This work introduces a unified hardware abstraction—termed the Position Graph—and proposes SHAPER, a novel heuristic scheduling algorithm that pioneers the adaptation of advanced superconducting-platform compilation techniques to the trapped-ion architecture. The approach integrates permutation-aware qubit mapping with physical-constraint-driven instruction generation. Contribution/Results: Evaluated on realistic trapped-ion hardware, our method successfully compiles complex circuits that fail under existing state-of-the-art (SOTA) compilers. It achieves an average 14% speedup in scheduling time, with peak improvements reaching 69%, thereby significantly overcoming current performance bottlenecks in trapped-ion quantum circuit compilation.

This work addresses the prolonged development cycle and limited adaptability of ion-transport compilers in complex trapped-ion quantum computing architectures. To overcome these challenges, the authors propose an automated compiler generation method leveraging large language models (Claude Opus 4.7 and Fable 5). Through prompt engineering and a progressive seed-code migration strategy, the approach autonomously generates and iteratively optimizes high-performance compilers tailored to diverse hardware topologies—including linear traps, junctioned arrays, and arbitrary connected graphs—using only textual specifications and without manual algorithmic intervention. Experimental results demonstrate that this methodology reduces compiler development time from months to days, achieves up to a 76% reduction in ion transport steps across multiple architectures, and delivers order-of-magnitude performance improvements in highly connected trap configurations.

This work addresses the high-dimensional optimization challenge in scaling multi-ion shuttling for modular ion-trap quantum chips by introducing reinforcement learning to ion transport control for the first time. The proposed approach learns optimal shuttling policies directly through interaction with the physical system, eliminating reliance on handcrafted heuristics that often lack generalizability. It establishes an efficient and scalable optimization framework applicable across diverse chip architectures. Experimental results demonstrate that the method reduces shuttling operations by up to 36.3% compared to state-of-the-art heuristic techniques and validates its effectiveness and versatility across multiple chip configurations.

To address the high manual design overhead and low execution fidelity/efficiency in mapping quantum algorithms to hardware, this paper proposes a cross-layer (algorithm–compiler–hardware) co-optimization framework. Methodologically, it pioneers the integration of deep reinforcement learning with graph neural networks to jointly automate quantum architecture search, logic synthesis, gate-level optimization, qubit mapping, and SWAP-based routing; it further introduces a superconducting-qubit hardware-adaptive modeling mechanism. Key contributions include: (1) establishing an AI-driven, end-to-end compilation optimization paradigm; (2) significantly reducing human intervention while improving circuit depth compression and quantum gate fidelity; and (3) empirically validating the feasibility and superior performance of the AI-enhanced compiler on medium-scale real superconducting quantum processors.

This work addresses the scalability and ion transport efficiency limitations of one-dimensional linear ion traps, which hinder the execution of large-scale quantum algorithms. The authors propose a two-dimensional segmented ion trap architecture based on quantum charge-coupled device (QCCD) principles, incorporating T-junctions and a fine-grained shuttling cost model that assigns distinct cost functions to operations on linear segments and junctions. They further develop a task-oriented co-compilation strategy that jointly optimizes architecture mapping and algorithm compilation. By adopting a modular chip layout, the approach significantly reduces transport overhead for representative quantum circuits such as the quantum Fourier transform and adders. Experimental results demonstrate that, under identical shuttling cost assumptions, the two-dimensional architecture outperforms its one-dimensional counterpart, with the performance advantage growing as the number of qubits increases, thereby confirming its superior scalability and efficiency.

This work addresses the critical bottleneck in compiling for trapped-ion quantum charge-coupled device (TI-QCCD) architectures, where qubit mapping and routing are constrained by physical limitations such as ion transport, trap capacity, and congestion. The authors propose a compilation framework based on a positional graph abstraction that uniformly models executable zones, movement paths, and routing constraints, integrating an enhanced SABRE-inspired heuristic search. Their approach innovatively introduces a relative movement scoring scheme and a memoized congestion-resolution mechanism, which substantially reduces redundant computations without altering scheduling decisions. This advancement significantly improves the scalability of SABRE-like algorithms on TI-QCCD platforms, offering an efficient and practical solution for qubit mapping and routing on heterogeneous quantum hardware.

This work addresses the challenge of compiling for modular multi-quantum processor architectures by jointly optimizing local qubit connectivity and inter-QPU communication to mitigate communication congestion, port overloading, and imbalanced boundary qubit allocation. The authors propose QuPort, a compilation framework that explicitly models QPU communication port constraints and link congestion at the compiler level for the first time. QuPort introduces a three-layer graph model—comprising a logical interaction graph, a physical coupling graph, and a QPU interconnect graph—and devises a TPCCAP partitioning method that simultaneously optimizes cut-edge distance, port overflow, and link congestion. Through an integrated pipeline featuring port-aware placement, remote gate extraction, and topology-aware scheduling, QuPort significantly reduces inter-QPU communication overhead, balances port utilization, and enhances compilation efficiency without relying on hardware-specific protocols.

This work addresses the absence of a pulse-level compilation layer in existing trapped-ion platforms capable of efficiently handling continuously parameterized gates within hybrid qubit-oscillator algorithms. To bridge this gap, we introduce HyPulse, a framework featuring a two-stage architecture combining offline optimization and online assembly to systematically solve the hardware-aware pulse synthesis problem for hybrid gates. HyPulse integrates an offline pulse optimization engine, a content-addressable caching mechanism, and an online program assembly module, offering compatibility with control backends such as DAX/ARTIQ and JaqalPaw/QSCOUT. It enables on-demand retrieval or automatic synthesis of dynamically parameterized gates, overcoming the limitations of static precompilation. Experimental results demonstrate that HyPulse can generate high-fidelity hybrid gate pulses on demand, significantly enhancing the executability and flexibility of hybrid quantum algorithms on trapped-ion platforms.

This work addresses the challenge of efficiently implementing quantum low-density parity-check (QLDPC) codes on semiconductor spin qubit platforms, which suffer from a lack of non-local connectivity. To overcome this limitation, the authors propose a co-scheduling algorithm for shuttling-based qubit architectures, drawing inspiration from robotic path planning and incorporating syndrome extraction circuits tailored to the platform’s shuttling noise model. This approach represents the first application of co-scheduling to QLDPC code implementation, expanding the feasible shuttling range by 5–10× and improving scheduling efficiency by up to 86% compared to hand-optimized strategies. Moreover, the method achieves logical error rates and coding efficiencies that surpass those of the surface code by several orders of magnitude.