achieve timing closure

This study addresses the fundamental differences and challenges in timing closure between FPGAs and ASICs. To tackle timing behavior divergence arising from their architectural heterogeneity, we propose the first cross-platform unified timing analysis framework, integrating static timing analysis, process-node-aware comparison, and silicon measurement validation. Using a comparative case study of Xilinx Kintex UltraScale+ FPGAs and 7 nm ASICs, we quantitatively characterize their timing performance boundaries: the ASIC achieves 45 ps setup and 35 ps hold times, while the FPGA attains 180 ps setup and 120 ps hold times—demonstrating substantial improvements in high-precision timing control for modern high-end FPGAs. The framework systematically elucidates the architecture–timing mapping relationship and enables performance- and programmability-aware co-design decisions in heterogeneous computing platforms. It provides both theoretical foundations and practical guidelines for high-performance reconfigurable systems.

Traditional simulation-based dynamic timing analysis struggles to balance accuracy and efficiency, and existing gate delay models lack sufficient expressiveness to enable precise, exhaustive path delay analysis for digital circuits. This work proposes a symbolic execution framework integrated with an analytical gate delay model that automatically generates symbolic delay expressions for all paths under a given input transition ordering. For the first time, it incorporates an analytical delay model accounting for both drafting effects and multi-input switching into symbolic execution. By employing a path-sensitive, goal-directed inference mechanism together with symbolic pruning strategies, the approach significantly enhances the completeness and precision of timing analysis while effectively mitigating the combinatorial explosion problem.

Conventional ASIC design flows largely neglect security, and commercial place-and-route (P&R) tools lack native support for modeling or optimizing security objectives. Method: This work introduces the first security-aware, zero-overhead ASIC physical synthesis flow, natively integrating hardware Trojan mitigation and physical attack resilience—against probing and fault injection—into a commercial P&R engine. It employs security-driven placement optimization, routing constraints, and cell substitution strategies, ensuring security convergence without compromising timing, area, or power. Contribution/Results: Evaluated on the ISPD’22 benchmark suite, the flow achieves state-of-the-art security metrics with negligible design overhead. All proposed methodologies and associated protection circuits are fully open-sourced, enabling reproducibility and community adoption.

This study addresses the challenge of systematically comparing timing behavior of RISC-V processors across heterogeneous technology platforms—specifically, 20 nm FPGAs versus 7 nm FinFET ASICs. We propose a microarchitectural-level, cross-platform timing attribution methodology that integrates static timing analysis (STA), PVT-corner statistical characterization, and pipeline-stage decoupled modeling. Our approach establishes a three-component decomposition framework—logic, routing, and clock—and precisely localizes timing-critical transitions to individual pipeline stages. For the first time, we reveal that FPGA timing is dominated by routing parasitics and topology sensitivity, yielding wide yet scattered timing margins; in contrast, ASIC timing is governed by combinational logic depth and PVT stability, resulting in narrow, concentrated margins. Quantitatively, we identify the EX→MEM stage transition as the common critical path across both platforms. Based on this insight, we formulate predictive, heterogeneity-aware design guidelines for timing convergence.

This work addresses the lack of a unified, cross-abstraction-layer benchmark for evaluating hardware design agents, which hinders assessment of end-to-end design convergence from specification to GDS. We propose CLOSER-Bench, the first evaluation protocol explicitly designed for budget-constrained, multi-stage hardware synthesis. It introduces paired tasks—spec-to-RTL, RTL-to-GDS, and spec-to-GDS—under a common objective, recording tool invocation trajectories to assess final quality, intermediate progress, resource overhead, and cross-stage recovery capability. Leveraging open-source toolchains including Verilator, Yosys, and OpenROAD within the Harbor agent framework, we validate the end-to-end workflow across ten tasks. Our experiments demonstrate that advanced agents significantly outperform baselines in joint verification-convergence tasks and successfully achieve full RTL-to-GDS closure for an AXI/DMA accelerator.

Although two-phase clocking offers advantages in timing margin and flexibility, its adoption in RTL implementation and static timing closure has been hindered by the absence of an automated design flow. This work presents the first fully automated two-phase clocking methodology integrated into OpenROAD Flow Scripts, which automatically transforms flip-flop-based RTL into latch-based two-phase implementations. The flow encompasses technology mapping (Yosys), retiming (ABC), dual-clock-tree synthesis, functional correctness verification, and end-to-end RTL-to-GDS physical implementation. It supports both clock-gating and feedback-multiplexer latch architectures; the clock-gating variant reduces power consumption by 29.2% on average and halves the latch count. By enabling time borrowing, the proposed approach successfully achieves timing convergence on critical paths where the original flip-flop design fails to meet timing constraints.