develop embedded software

Embedded systems face significant challenges in hardware-software co-development, including strong hardware dependencies, stringent real-time and safety requirements, and poor compatibility with conventional CI/CD practices. Method: Through a systematic literature review of 20 academic and industrial studies, we establish the first DevOps practice taxonomy specifically for embedded systems; propose a hardware-aware CI/CD framework supporting closed-loop hardware testing, resource-constrained execution, and safety compliance; and identify and address critical gaps in deployment automation and observability. Contribution/Results: We synthesize toolchain design, automated testing strategies, pipeline lightweighting, and firmware security practices into a structured knowledge framework. This work provides both a theoretical foundation and concrete research directions for academia, and delivers a reusable, industry-applicable methodology for realizing Embedded DevOps.

To address critical challenges in SoC design—including ambiguous system-level modeling semantics, poor interoperability across heterogeneous computational models (e.g., dataflow and neural networks), and the decoupling of design-space exploration from verification—this paper proposes a co-communication mechanism ensuring semantic consistency across multiple models. The approach establishes an integrated toolchain supporting system-level modeling, simulation-driven verification, hardware-software co-design space exploration, and joint power-performance analysis. Innovatively, it unifies dataflow modeling with system-level abstractions to enable functional correctness verification and quantitative energy-efficiency evaluation for representative applications such as video processing and AI acceleration. Experimental results demonstrate that the methodology significantly improves early-stage SoC design iteration efficiency and enhances the reliability of architectural decision-making.

To address the low efficiency and error-proneness of manual development and integration of software components in embedded systems, this paper proposes an Abstract Syntax Tree (AST)-driven Retrieval-Augmented Generation (RAG) method for fully automated, zero-intervention generation and formal verification of microcontroller Hardware Abstraction Layer (HAL) code. Focusing on the STM32F407 GPIO module, the approach integrates AST-based semantic analysis, RAG-enabled dynamic knowledge retrieval, static code verification, and HAL framework adaptation to ensure syntactic correctness, semantic consistency, and platform compatibility. Experimental evaluation demonstrates that the generated HAL code is functionally complete, directly compilable and flashable, and passes comprehensive functional testing on real hardware across all operational scenarios, achieving 98.7% accuracy. This work establishes the first end-to-end pipeline for automated HAL code generation coupled with formal verification in embedded systems.

Identifying critical safety constraints from the vast number of Hardware Abstraction Layer (HAL) interfaces in embedded systems remains challenging, hindering effective fault prevention. Method: This paper proposes a fault-prevention-oriented requirement prioritization approach. Its core innovation is the formal definition of “indisputable relevance,” transforming hardware access constraint identification into a verifiable formal verification problem. The method models HAL interfaces, semantically analyzes real-world failure reports, and leverages model checkers (e.g., CBMC) to automatically generate mathematical proofs—thereby extracting and verifying constraints strongly correlated with system failures or hardware damage. Results: Evaluated on three industrial-grade failure cases involving the SPI bus spidev HAL, the approach successfully identified and formally verified critical requirements. Experimental results demonstrate its feasibility and effectiveness, establishing a novel, verifiable, and traceable paradigm for requirements engineering in high-reliability embedded systems.

ASIC development faces challenges in IP reuse and lacks integrated hardware-software co-verification and unified build infrastructure. Method: This paper introduces SoCMake—the first unified SoC build system supporting cross-compilation of Chisel/SystemRDL hardware descriptions with C/C++/assembly code. It integrates RTL generation, simulation, firmware compilation, and SoC configuration into a single workflow, overcoming the limited software compilation support of conventional hardware build tools. By deeply embedding SystemC, the RISC-V toolchain, and CMake’s extensibility framework, SoCMake enables automated, abstraction-level–aware co-building across hardware description → RTL → firmware. Contribution/Results: SoCMake has successfully accelerated iterative deployment of radiation-tolerant RISC-V SoCs in high-energy physics applications. After open-sourcing, it has become a de facto standard for generic SoC generation, reducing overall SoC development time by over 40% in empirical evaluations.

This study systematically evaluates whether Rust can compete with C in performance and resource efficiency for microcontroller firmware development and assesses its industrial viability. Two teams independently implemented identical industrial IoT firmware—one in Rust and the other in C—and key metrics including development effort, memory footprint, and execution speed were compared on real hardware. This work presents the first systematic comparison of the two languages in a genuine industrial context and introduces Ariel OS, a lightweight Rust-based runtime. Empirical results demonstrate that Rust matches or exceeds C in both resource utilization and execution performance, while Ariel OS exhibits a smaller binary footprint, collectively establishing Rust as a reliable and competitive choice for microcontroller firmware development.

Debugging embedded programs is notoriously challenging due to tight software-hardware coupling, and existing tools often rely on external hardware probes or serial logging, resulting in low efficiency. This work proposes Inline, a novel programming tool that, for the first time, enables real-time inline visualization of hardware logs directly within source code. It introduces a domain-specific expression language to support programmable manipulation of logs, allowing developers to intuitively trace execution flow and precisely localize faults. Seamlessly integrated into standard embedded development environments, Inline significantly lowers the barrier to effective debugging. A user study with twelve participants demonstrates marked improvements in both debugging efficiency and accuracy when using the tool.

This work addresses the challenges in edge and embedded application development—namely, heterogeneous software stacks, multi-language runtimes, and difficult debugging—which lead to rigid deployment workflows and complex fault diagnosis. To overcome these limitations, the paper proposes a novel architecture enabling unified end-edge-cloud development. Its core components include a single programming language, a retargetable runtime system, a local recording and replay mechanism for distributed events, and a cross-platform deployment framework. This design breaks down traditional debugging barriers in edge–cloud collaborative development, facilitating seamless scalability, consistent testing, and flexible deployment across heterogeneous environments. Evaluation of the prototype system demonstrates that the proposed approach significantly simplifies deployment procedures and enhances fault diagnosis efficiency.

This work addresses the challenge that existing AI methods struggle to jointly model the tight coupling between software logic and physical hardware behavior in hardware-in-the-loop (HIL) development of embedded and IoT systems, often leading to deployment failures. To tackle this, the authors propose a skill-oriented agent architecture tailored for HIL scenarios and introduce IoT-SkillsBench, a novel real-hardware evaluation benchmark. The framework systematically assesses AI agents across multiple platforms, peripherals, and task complexities through three agent configurations enhanced by skill augmentation, structured expert knowledge injection, and real-hardware validation. Experimental results demonstrate that, over 378 real-world deployments, agents equipped with human-expert-derived skills achieve near-perfect cross-platform task success rates, substantially outperforming baseline approaches.

Automotive electronic control units (ECUs) are intricate systems with hundreds of individual functions, numerous software components, and multiple interdependent tasks. A prevalent structural pattern in these systems are so-called cause-effect chains. While significant research efforts have been dedicated to the temporal analysis and optimization of these chains, particularly minimizing data age and function response times, other crucial non-functional properties remain relatively underexplored. In particular, the safety integrity level (SIL) classification substantially influences the system design by determining task colocation strategies. Improper sharing of functions or interweaving tasks with different safety levels can compromise the integrity of critical functions. Additionally, AUTOSAR basic software (BSW) (e.g. OS, runtime environment, communication stacks, or diagnostics) introduces complexity that varies based on task characteristics and SIL categories. Furthermore, memory requirements present another critical challenge, given the diversity of memory architectures and SIL-specific dependencies that strongly constrain task allocations. This paper thoroughly characterizes a real-world automotive application, describing an automotive application based on SIL constraints, the impact of basic software, and memory requirements. In this context, the Driverator configuration framework is introduced for scalable system analysis.