embedded systems

ASIC development faces challenges in IP reuse and lacks integrated hardware-software co-verification and unified build infrastructure. Method: This paper introduces SoCMake—the first unified SoC build system supporting cross-compilation of Chisel/SystemRDL hardware descriptions with C/C++/assembly code. It integrates RTL generation, simulation, firmware compilation, and SoC configuration into a single workflow, overcoming the limited software compilation support of conventional hardware build tools. By deeply embedding SystemC, the RISC-V toolchain, and CMake’s extensibility framework, SoCMake enables automated, abstraction-level–aware co-building across hardware description → RTL → firmware. Contribution/Results: SoCMake has successfully accelerated iterative deployment of radiation-tolerant RISC-V SoCs in high-energy physics applications. After open-sourcing, it has become a de facto standard for generic SoC generation, reducing overall SoC development time by over 40% in empirical evaluations.

To address critical challenges in SoC design—including ambiguous system-level modeling semantics, poor interoperability across heterogeneous computational models (e.g., dataflow and neural networks), and the decoupling of design-space exploration from verification—this paper proposes a co-communication mechanism ensuring semantic consistency across multiple models. The approach establishes an integrated toolchain supporting system-level modeling, simulation-driven verification, hardware-software co-design space exploration, and joint power-performance analysis. Innovatively, it unifies dataflow modeling with system-level abstractions to enable functional correctness verification and quantitative energy-efficiency evaluation for representative applications such as video processing and AI acceleration. Experimental results demonstrate that the methodology significantly improves early-stage SoC design iteration efficiency and enhances the reliability of architectural decision-making.

Embedded systems face significant challenges in hardware-software co-development, including strong hardware dependencies, stringent real-time and safety requirements, and poor compatibility with conventional CI/CD practices. Method: Through a systematic literature review of 20 academic and industrial studies, we establish the first DevOps practice taxonomy specifically for embedded systems; propose a hardware-aware CI/CD framework supporting closed-loop hardware testing, resource-constrained execution, and safety compliance; and identify and address critical gaps in deployment automation and observability. Contribution/Results: We synthesize toolchain design, automated testing strategies, pipeline lightweighting, and firmware security practices into a structured knowledge framework. This work provides both a theoretical foundation and concrete research directions for academia, and delivers a reusable, industry-applicable methodology for realizing Embedded DevOps.

Identifying critical safety constraints from the vast number of Hardware Abstraction Layer (HAL) interfaces in embedded systems remains challenging, hindering effective fault prevention. Method: This paper proposes a fault-prevention-oriented requirement prioritization approach. Its core innovation is the formal definition of “indisputable relevance,” transforming hardware access constraint identification into a verifiable formal verification problem. The method models HAL interfaces, semantically analyzes real-world failure reports, and leverages model checkers (e.g., CBMC) to automatically generate mathematical proofs—thereby extracting and verifying constraints strongly correlated with system failures or hardware damage. Results: Evaluated on three industrial-grade failure cases involving the SPI bus spidev HAL, the approach successfully identified and formally verified critical requirements. Experimental results demonstrate its feasibility and effectiveness, establishing a novel, verifiable, and traceable paradigm for requirements engineering in high-reliability embedded systems.

Emerging edge and cloud AI applications demand high-energy-efficiency computing, yet conventional embedded and datacenter architectures struggle to simultaneously achieve high performance and energy efficiency. Method: This work systematically surveys 15 years of approximate computing research, introducing the first full-stack taxonomy—spanning programs, compilers, circuits, accelerators, and memory—along with rigorously defined core terminology and design principles; it further proposes a unified evaluation framework for quantitative, cross-layer trade-off analysis between performance and power consumption. Contribution/Results: The study delivers the first authoritative survey on approximate computing (Part I), addressing a critical gap in systematic, domain-wide reviews. By establishing foundational taxonomies and evaluation methodologies, it provides both theoretical grounding and practical guidance for algorithm–architecture co-optimization, thereby advancing energy-efficient computing for AI workloads.

This study systematically evaluates whether Rust can compete with C in performance and resource efficiency for microcontroller firmware development and assesses its industrial viability. Two teams independently implemented identical industrial IoT firmware—one in Rust and the other in C—and key metrics including development effort, memory footprint, and execution speed were compared on real hardware. This work presents the first systematic comparison of the two languages in a genuine industrial context and introduces Ariel OS, a lightweight Rust-based runtime. Empirical results demonstrate that Rust matches or exceeds C in both resource utilization and execution performance, while Ariel OS exhibits a smaller binary footprint, collectively establishing Rust as a reliable and competitive choice for microcontroller firmware development.

This work addresses the inefficiencies and semantic inconsistencies arising from separately implementing driver and monitor programs in traditional hardware module testing. To overcome this, the authors propose a domain-specific language (DSL) tailored to hardware communication protocols, which enables the unified specification of both driver and monitor logic through an imperative syntax, thereby ensuring their semantic consistency for the first time. Building upon this DSL, they develop a prototype tool that leverages waveform parsing and transaction-level trace inference techniques to accurately reconstruct protocol-compliant transaction sequences from raw signal waveforms. Experimental results demonstrate that the approach significantly improves development efficiency, with further validation planned on real-world interconnect protocols such as Wishbone and AXI-Stream.

This study addresses the inherent challenge in hardware design of balancing complexity management with model accuracy. To this end, it proposes an abstraction-centric methodology that associates discretization techniques with pre-clustered elements, such as transistors. By integrating lumped modeling, value discretization, and time discretization, the approach establishes a well-defined hierarchy of abstractions. The primary contribution of this work is a standardized design methodology that enhances productivity by simplifying model complexity and improving simulation efficiency while defining effective constraints. Consequently, this framework significantly strengthens the capacity to manage complex systems in digital design, thereby advancing overall engineering productivity.

This study addresses the NP-hard problem of hardware/software partitioning in computing architectures. Leveraging the directed pathwidth of task graphs, this work proposes a novel family of problem formulations that subsumes existing models, along with exact fixed-parameter tractable (FPT) algorithms. Methodologically, by integrating directed pathwidth analysis, FPT theory, and integer linear programming (ILP), the proposed approach achieves exact and efficient solutions for this problem family. The primary theoretical contribution lies in extending the modeling framework for hardware/software partitioning and establishing its fixed-parameter tractability. Empirically, experiments on real-world application scenarios demonstrate that the proposed method achieves up to a 200-fold speedup over general-purpose ILP solvers such as Gurobi, highlighting its practical efficacy and computational advantage.

This work addresses the limitations of conventional system-on-chip (SoC) architectures that employ isolated, component-level single-event upset (SEU) mitigation techniques, which often neglect critical paths such as interconnects and voting logic, thereby creating single points of failure. To overcome this, the authors propose an overlapping cooperative fault-tolerance strategy that integrates tailored architectural-level protections for processor cores, memory, interconnects, and voting logic, achieving end-to-end, gap-free SEU resilience. Evaluated on a RISC-V microcontroller SoC through both fault-injection simulations and physical implementation, the approach demonstrates over 99.9% fault tolerance at both RTL and post-layout netlist levels. Compared to fine-grained triple modular redundancy and other global redundancy schemes, the proposed method reduces area overhead by 22%, significantly enhancing both reliability and resource efficiency.