silicon bring-up

This work addresses the lack of cost-effective, high-precision power measurement solutions for embedded systems, given the high expense and inflexibility of industrial semiconductor test equipment. The authors propose and implement a compact, open-source hardware and software-based system-level power profiling platform that integrates a Raspberry Pi controller, a high-accuracy current sensor, and a microcontroller-based device under test (DUT). A lightweight HTTP interface enables automated firmware deployment, synchronized execution, and remote control. By uniquely combining low-cost open-source hardware with an automated testing workflow, the platform achieves high-resolution current acquisition and supports energy-efficiency benchmarking and regression testing across multiple firmware variants. This significantly enhances the scalability, reproducibility, and practicality of power analysis for embedded systems, making it well-suited for research, prototyping, and educational applications.

ASIC development faces challenges in IP reuse and lacks integrated hardware-software co-verification and unified build infrastructure. Method: This paper introduces SoCMake—the first unified SoC build system supporting cross-compilation of Chisel/SystemRDL hardware descriptions with C/C++/assembly code. It integrates RTL generation, simulation, firmware compilation, and SoC configuration into a single workflow, overcoming the limited software compilation support of conventional hardware build tools. By deeply embedding SystemC, the RISC-V toolchain, and CMake’s extensibility framework, SoCMake enables automated, abstraction-level–aware co-building across hardware description → RTL → firmware. Contribution/Results: SoCMake has successfully accelerated iterative deployment of radiation-tolerant RISC-V SoCs in high-energy physics applications. After open-sourcing, it has become a de facto standard for generic SoC generation, reducing overall SoC development time by over 40% in empirical evaluations.

This study addresses the lack of systematic research on generative artificial intelligence (GenAI) across the full lifecycle of printed circuit board (PCB) development by proposing the first GenAI application taxonomy tailored to the PCB domain. Spanning stages from supply chain management and specification definition to circuit design, layout optimization, verification testing, and assembly distribution, the framework is developed through a systematic literature review and taxonomic analysis. The work critically examines the applicability and limitations of GenAI in hardware design automation, identifying key challenges such as data scarcity and insufficient toolchain integration. Beyond highlighting the substantial potential of GenAI in PCB design and testing, this research establishes a clear technical roadmap to guide future investigations in the field.

To address low efficiency, insufficient coverage, and poor RTL bug detection in FSM-based chip functional verification, this paper proposes an EDA-feedback-driven, closed-loop LLM testbench generation method. Initial testbenches are generated using GPT-3.5 or GPT-4; then, real-time signal-level feedback—including code and state coverage metrics and error diagnostics—from commercial EDA tools (e.g., Synopsys VCS) is integrated into the prompt engineering process, enabling iterative refinement. This work pioneers deep integration of EDA tool feedback into the LLM generation pipeline, supporting coverage-guided automated test generation and concurrent RTL-level bug detection. Evaluated on multiple industrial-grade FSM designs, the method improves code and state coverage by 20–35% over baseline approaches and successfully identifies timing and control-logic bugs missed by manual verification. The approach significantly enhances both verification efficiency and reliability.

Existing SoC virtual platforms lack non-intrusive, runtime performance analysis tools for SystemC-TLM 2.0 simulations. Method: This paper proposes a lightweight, fully non-intrusive tracing framework that requires no source-code modification and does not rely on debug symbols. It integrates SystemC API hooking, dynamic binary instrumentation, and event-driven logging, ensuring cross-platform compatibility via standard APIs while supporting database persistence and visualization-enabled post-processing. Contribution/Results: We introduce the first fully non-intrusive TLM 2.0 tracing mechanism, enabling fine-grained, transaction-level behavioral capture without perturbing simulation logic. Experiments demonstrate complete tracing of the Linux boot process with an average runtime overhead below 3%, achieving high fidelity and practical usability. The framework significantly enhances performance analysis and debugging efficiency in hardware-software co-design workflows.

This work addresses the inefficiencies and semantic inconsistencies arising from separately implementing driver and monitor programs in traditional hardware module testing. To overcome this, the authors propose a domain-specific language (DSL) tailored to hardware communication protocols, which enables the unified specification of both driver and monitor logic through an imperative syntax, thereby ensuring their semantic consistency for the first time. Building upon this DSL, they develop a prototype tool that leverages waveform parsing and transaction-level trace inference techniques to accurately reconstruct protocol-compliant transaction sequences from raw signal waveforms. Experimental results demonstrate that the approach significantly improves development efficiency, with further validation planned on real-world interconnect protocols such as Wishbone and AXI-Stream.

This work addresses the inefficiencies of manual test planning in large-scale AI data center hardware verification, which suffers from low productivity, insufficient coverage, and poor reusability. The paper proposes the first hardware verification framework that integrates generative AI with multi-agent collaboration to automatically construct structured test plans from self-healing verification documents and bills of materials. The framework enables automated test case generation, intelligent coverage gap closure, and end-to-end traceability. Key technical innovations include input normalization, context-aware component classification, and fault mode synthesis, ensuring high portability across platforms. Experimental results on two production platforms demonstrate coverage improvements of 74.2% and 51.4%, respectively, reducing test plan development time from days to hours while achieving high expert acceptance in novel scenarios.

This study addresses the growing challenges traditional failure analysis methods face in the era of advanced packaging technologies—such as chiplets, hybrid bonding, and 3D stacking—by conducting an anonymous global survey of over 100 semiconductor design, packaging, and failure analysis organizations. The findings reveal that 69% of respondents prioritize heterogeneous integration products (mean importance score: 7.92/10), while 54% identify hybrid bonding as the most analytically challenging technique. A strong consensus emerges around the need for standardized data formats, with 83% of participants advocating for unified protocols, and high-resolution non-destructive imaging garners substantial support (mean score: 8.18/10). The research systematically identifies critical pain points in sample preparation and 3D structural inspection, offering empirical insights to guide industry standardization and technological innovation.